TY - GEN
T1 - 1-bit heuristic adaptive quantizer (HAQ) for on chip image compression in CMOS image sensors
AU - Barrow, Michael
AU - Bermak, Amine
AU - Chen, Shoushun
PY - 2011
Y1 - 2011
N2 - This paper presents an algorithm for implementing a single bit adaptive quantizer based on fast boundary adaptation rule (FBAR). The peak signal to noise ratio (PSNR) gain and performance gain of the algorithm over prior designs is found to be larger than that displayed by prior art compared with a reference FBAR implementation. A maximum increase of 1.44db was seen. In addition, the new design facilitates an improved bits per pixel ratio (bpp) when integrated with the QTD compressor utilized in previous prototypes. The presented algorithm is hardware friendly and designed for low power implementation, with simulation results also showing an improvement of relative energy cost over previous work. Experimental evidence for image sizes ranging from 6464 pixels to 512512 pixels and the heuristic adaptive quantizer (HAQ) algorithm are detailed in this paper.
AB - This paper presents an algorithm for implementing a single bit adaptive quantizer based on fast boundary adaptation rule (FBAR). The peak signal to noise ratio (PSNR) gain and performance gain of the algorithm over prior designs is found to be larger than that displayed by prior art compared with a reference FBAR implementation. A maximum increase of 1.44db was seen. In addition, the new design facilitates an improved bits per pixel ratio (bpp) when integrated with the QTD compressor utilized in previous prototypes. The presented algorithm is hardware friendly and designed for low power implementation, with simulation results also showing an improvement of relative energy cost over previous work. Experimental evidence for image sizes ranging from 6464 pixels to 512512 pixels and the heuristic adaptive quantizer (HAQ) algorithm are detailed in this paper.
UR - http://www.scopus.com/inward/record.url?scp=84863054895&partnerID=8YFLogxK
U2 - 10.1109/ISICir.2011.6131937
DO - 10.1109/ISICir.2011.6131937
M3 - Conference contribution
AN - SCOPUS:84863054895
SN - 9781612848648
T3 - 2011 International Symposium on Integrated Circuits, ISIC 2011
SP - 613
EP - 616
BT - 2011 International Symposium on Integrated Circuits, ISIC 2011
T2 - 2011 International Symposium on Integrated Circuits, ISIC 2011
Y2 - 12 December 2011 through 14 December 2011
ER -