A 10-GHz Low-Power Serial Digital Majority Voter Based on Moving Accumulative Sign Filter in a PS-/PI-Based CDR

In this article, a moving accumulative sign filter (MASF) voter model and a low-power serial voting circuit are proposed for high-speed clock data recovery (CDR). Different from the previously reported parallel voter and moving average majority voter (MV), the proposed design is based on the MASF algorithm and adopts a two-stage voting structure. Only D-flip-flop (DFF) and basic logic gates are used to realize the serial voting function of the four continuous lead/lag/hold decision signals. The proposed MV realizes the signal processing of the four-phase error information without using traditional gain and quantization operations. In addition, by eliminating the redundant output state, the input noise of the digital filter of CDR can be reduced, which could also reduce the power consumption of the subsequent circuits due to less logical flips. As a result, the proposed serial MV can operate at a half baud rate in a high-speed CDR and it can reduce the chip area by removing the demultiplexer unit and the moving average filter. The proposed MV circuit is implemented for a high-speed CDR using a 40-nm CMOS process, which shows a 12-GHz maximum operating speed. The measured power consumption of the whole voter at 10 GHz is only 0.55 mW and the core chip area is $8.6\,\times \,25.4\,\,\mu \text{m}^{2}$.