A 12~14.6GHz Fractional-N Sub-Sampling PLL for Wavelength Modulation Spectroscopy of CSMCs

Shuting Peng, Bo Wang, Cheng Wang*

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This paper presents a fractional-N sub-sampling PLL (SSPLL) for wavelength modulation spectroscopy of chip-scale molecular clocks (CSMCs). The proposed SSPLL adopts a 5-bit vector modulator (VM) based phase-interpolator (PI) and a 5-bit digital-to-time converter (DTC) for in-band phase noise suppression. The proposed 5-bit VM based PI achieves high phase linearity with INL/DNL < 0.25 LSB. It reduces the required dynamic range and intrinsic jitter of the DTC. According to the simulation, the SSPLL spans from 12GHz to 14.6GHz with a rms jitter of 99.4fs, The DC power consumption is 26.7mW. The SSPLL's figure-of-the-merit (FoM) achieves -245.8 dB.

Original languageEnglish
Title of host publication16th UK-Europe-China Workshop on Millimetre Waves and Terahertz Technologies, UCMMT 2023 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9798350339406
DOIs
Publication statusPublished - 2023
Event16th UK-Europe-China Workshop on Millimetre Waves and Terahertz Technologies, UCMMT 2023 - Guangzhou, China
Duration: 31 Aug 20233 Sept 2023

Publication series

Name16th UK-Europe-China Workshop on Millimetre Waves and Terahertz Technologies, UCMMT 2023 - Proceedings

Conference

Conference16th UK-Europe-China Workshop on Millimetre Waves and Terahertz Technologies, UCMMT 2023
Country/TerritoryChina
CityGuangzhou
Period31/08/233/09/23

Keywords

  • CSMC
  • DTC
  • PI
  • SSPLL

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