TY - GEN
T1 - A 2.2μW 15b incremental delta-sigma ADC with output-driven input segmentation
AU - Wang, Bo
AU - Law, Man Kay
AU - Mohamad, Saqib
AU - Bermak, Amine
N1 - Publisher Copyright:
© 2016 IEEE.
PY - 2016/3/7
Y1 - 2016/3/7
N2 - A micro-power incremental delta-sigma (I-ΣS) ADC is presented. This ADC uses its decimation filter's output to estimate the input signal level and dynamically adjusts the modulator feedback voltage, thereby reducing the integrator input range and power. For further power saving, integrator time-multiplexing is also employed. Fabricated in 0.18μm CMOS, the 0.12mm2 ADC consumes 2.16μW at a conversion speed of 85S/s, 15.3b resolution and-2/1.5LSB INL.
AB - A micro-power incremental delta-sigma (I-ΣS) ADC is presented. This ADC uses its decimation filter's output to estimate the input signal level and dynamically adjusts the modulator feedback voltage, thereby reducing the integrator input range and power. For further power saving, integrator time-multiplexing is also employed. Fabricated in 0.18μm CMOS, the 0.12mm2 ADC consumes 2.16μW at a conversion speed of 85S/s, 15.3b resolution and-2/1.5LSB INL.
KW - dual-feedback ΣS modulator
KW - incremental delta-sigma ADC
KW - integrator multiplexing
KW - low power ADC
UR - http://www.scopus.com/inward/record.url?scp=84996636567&partnerID=8YFLogxK
U2 - 10.1109/ASPDAC.2016.7427975
DO - 10.1109/ASPDAC.2016.7427975
M3 - Conference contribution
AN - SCOPUS:84996636567
T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
SP - 7
EP - 8
BT - 2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016
Y2 - 25 January 2016 through 28 January 2016
ER -