A 33.6nW Capacitively Coupled Chopper Amplifier with Stacked Input-Boosted Gate-and-Bulk-Driven Inverter Achieving 0.59 NEF and 0.42 PEF in 180nm CMOS

The overall noise in a sensor read-out circuit is typically dominated by the front-end-amplifier. Achieving low noise often requires high power due to the inherent tradeoff between transconductance G_m and bias current I_d of the transistor. Developing techniques to mitigate this noise-power tradeoff is crucial for power- and energy-constrained systems. Inverter-based amplifier can effectively double the G_m/I_d ratio through two-fold current reuse. In [1], the input-boosted inverter-based amplifier achieved both current reuse and input boosting simultaneously, resulting in a four-fold improvement in G_m/I_d. Stacking amplifiers can further increase the ratio of current reuse, with one design achieving six-fold current reuse and a corresponding six-fold boost in G_m/I_d [2]. However, the power-consuming current summation branch reduces the power efficiency. Inserting AC-coupling capacitors at the outputs of the stacked amplifier can eliminate the current summation branch, and a ten-fold gm/ld boosting was reported [3]. Despite these advancements, the supply voltage of the stacking structure increases with the number of stacking stages, which impedes further improvement in the power-efficiency factor (PEF). This work introduces a 3-stacking topology with six-fold current reuse using an input-boosted gate-and-bulk-driven inverter-based amplifier, effectively increasing G_m and the number of stacking stages for a given power budget. Fabricated in 0.18 μm CMOS, the proposed capacitively coupled chopper instrumentation amplifier (CCIA) achieves an integrated input-referred-noise (IRN) of 2.16 μVrms within a bandwidth of 550 Hz, resulting in a noise-efficiency factor (NEF) and PEF of 0.59 and 0.42, respectively. Compared to the CCIA with an input-boosted inverter-based amplifier [1], the NEF and PEF are improved by approximately 40% and 27%, respectively. Even compared to a topology with ten-fold current reuse [3], the NEF and PEF are enhanced by about 31% and 57%, respectively, with only six-fold current reuse.