A 64 × 64 CMOS digital pixel array based on pulse width analogue to digital conversion, with on chip linearising circuit

Alistair J. Kitchen; Amine Bermak; Abdessalam Bouzerdoum

doi:10.1117/12.525558

A 64 × 64 CMOS digital pixel array based on pulse width analogue to digital conversion, with on chip linearising circuit

Alistair J. Kitchen^*, Amine Bermak, Abdessalam Bouzerdoum

^*Corresponding author for this work

Research output: Contribution to journal › Conference article › peer-review

Abstract

This paper describes a 64 × 64 digital pixel array employing a pulse width analogue to digital conversion scheme. Each pixel contains a photodiode sensor, comparator and memory, and in conjunction with a central control circuit performs the analogue to digital conversion, by timing a pulse generated by the photodiode/comparator circuit. The control circuit produces data which compensates for this nonlinear relationship, resulting in a pixel parallel ADC operation. The digital image data can be read from the array non-destructively, with random access. The array is constructed in a standard 0.35μm, 3.3 V digital CMOS process.

Original language	English
Pages (from-to)	163-171
Number of pages	9
Journal	Proceedings of SPIE - The International Society for Optical Engineering
Volume	5274
DOIs	https://doi.org/10.1117/12.525558
Publication status	Published - 2004
Externally published	Yes
Event	Microelectronics: Design, Technology and Packaging - Perth, WA, Australia Duration: 10 Dec 2003 → 12 Dec 2003

Keywords

CMOS pixel
DPS
Pixel

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10.1117/12.525558

Cite this

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title = "A 64 × 64 CMOS digital pixel array based on pulse width analogue to digital conversion, with on chip linearising circuit",

abstract = "This paper describes a 64 × 64 digital pixel array employing a pulse width analogue to digital conversion scheme. Each pixel contains a photodiode sensor, comparator and memory, and in conjunction with a central control circuit performs the analogue to digital conversion, by timing a pulse generated by the photodiode/comparator circuit. The control circuit produces data which compensates for this nonlinear relationship, resulting in a pixel parallel ADC operation. The digital image data can be read from the array non-destructively, with random access. The array is constructed in a standard 0.35μm, 3.3 V digital CMOS process.",

keywords = "CMOS pixel, DPS, Pixel",

author = "Kitchen, {Alistair J.} and Amine Bermak and Abdessalam Bouzerdoum",

year = "2004",

doi = "10.1117/12.525558",

language = "English",

volume = "5274",

pages = "163--171",

journal = "Proceedings of SPIE - The International Society for Optical Engineering",

issn = "0277-786X",

publisher = "SPIE",

note = "Microelectronics: Design, Technology and Packaging ; Conference date: 10-12-2003 Through 12-12-2003",

}

A 64 × 64 CMOS digital pixel array based on pulse width analogue to digital conversion, with on chip linearising circuit. / Kitchen, Alistair J.; Bermak, Amine ; Bouzerdoum, Abdessalam.
In: Proceedings of SPIE - The International Society for Optical Engineering, Vol. 5274, 2004, p. 163-171.

Research output: Contribution to journal › Conference article › peer-review

TY - JOUR

T1 - A 64 × 64 CMOS digital pixel array based on pulse width analogue to digital conversion, with on chip linearising circuit

AU - Kitchen, Alistair J.

AU - Bermak, Amine

AU - Bouzerdoum, Abdessalam

PY - 2004

Y1 - 2004

N2 - This paper describes a 64 × 64 digital pixel array employing a pulse width analogue to digital conversion scheme. Each pixel contains a photodiode sensor, comparator and memory, and in conjunction with a central control circuit performs the analogue to digital conversion, by timing a pulse generated by the photodiode/comparator circuit. The control circuit produces data which compensates for this nonlinear relationship, resulting in a pixel parallel ADC operation. The digital image data can be read from the array non-destructively, with random access. The array is constructed in a standard 0.35μm, 3.3 V digital CMOS process.

AB - This paper describes a 64 × 64 digital pixel array employing a pulse width analogue to digital conversion scheme. Each pixel contains a photodiode sensor, comparator and memory, and in conjunction with a central control circuit performs the analogue to digital conversion, by timing a pulse generated by the photodiode/comparator circuit. The control circuit produces data which compensates for this nonlinear relationship, resulting in a pixel parallel ADC operation. The digital image data can be read from the array non-destructively, with random access. The array is constructed in a standard 0.35μm, 3.3 V digital CMOS process.

KW - CMOS pixel

KW - DPS

KW - Pixel

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U2 - 10.1117/12.525558

DO - 10.1117/12.525558

M3 - Conference article

AN - SCOPUS:2442549562

SN - 0277-786X

VL - 5274

SP - 163

EP - 171

JO - Proceedings of SPIE - The International Society for Optical Engineering

JF - Proceedings of SPIE - The International Society for Optical Engineering

T2 - Microelectronics: Design, Technology and Packaging

Y2 - 10 December 2003 through 12 December 2003

ER -

A 64 × 64 CMOS digital pixel array based on pulse width analogue to digital conversion, with on chip linearising circuit

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Keywords

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