A 96 × 64 Intelligent digital pixel array with extended binary stochastic arithmetic

Tarik Hammadou; Magnus Nilson; Amine Bermak; Philip Ogunbona

A 96 × 64 Intelligent digital pixel array with extended binary stochastic arithmetic

Tarik Hammadou^*, Magnus Nilson, Amine Bermak, Philip Ogunbona

^*Corresponding author for this work

Research output: Contribution to journal › Conference article › peer-review

12 Citations (Scopus)

Abstract

A chip architecture that integrates an optical sensor and a pixel level processing element based on binary stochastic arithmetic is proposed. The optical sensor is formed by an array of fully connected pixels, and each pixel contains a sensing element and a Pulse Frequency Modulator (PFM) converting the incident light to bit streams of identical pulses. The processing element is based on binary stochastic arithmetic to perform signal processing operations on the focal plane VLSI circuit. A 96 × 64 CMOS image sensor is fabricated using 0.5μm CMOS technology and achieves 29 × 29μm pixel size at 15% fill factor.

Original language	English
Pages (from-to)	IV772-IV775
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	4
Publication status	Published - 2003
Externally published	Yes
Event	Proceedings of the 2003 IEEE International Symposium on Circuits and Systems - Bangkok, Thailand Duration: 25 May 2003 → 28 May 2003

Cite this

@article{c9eee2f0855548f1af17bbdccca4b76f,

title = "A 96 × 64 Intelligent digital pixel array with extended binary stochastic arithmetic",

abstract = "A chip architecture that integrates an optical sensor and a pixel level processing element based on binary stochastic arithmetic is proposed. The optical sensor is formed by an array of fully connected pixels, and each pixel contains a sensing element and a Pulse Frequency Modulator (PFM) converting the incident light to bit streams of identical pulses. The processing element is based on binary stochastic arithmetic to perform signal processing operations on the focal plane VLSI circuit. A 96 × 64 CMOS image sensor is fabricated using 0.5μm CMOS technology and achieves 29 × 29μm pixel size at 15% fill factor.",

author = "Tarik Hammadou and Magnus Nilson and Amine Bermak and Philip Ogunbona",

year = "2003",

language = "English",

volume = "4",

pages = "IV772--IV775",

journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

issn = "0271-4310",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "Proceedings of the 2003 IEEE International Symposium on Circuits and Systems ; Conference date: 25-05-2003 Through 28-05-2003",

}

TY - JOUR

T1 - A 96 × 64 Intelligent digital pixel array with extended binary stochastic arithmetic

AU - Hammadou, Tarik

AU - Nilson, Magnus

AU - Bermak, Amine

AU - Ogunbona, Philip

PY - 2003

Y1 - 2003

N2 - A chip architecture that integrates an optical sensor and a pixel level processing element based on binary stochastic arithmetic is proposed. The optical sensor is formed by an array of fully connected pixels, and each pixel contains a sensing element and a Pulse Frequency Modulator (PFM) converting the incident light to bit streams of identical pulses. The processing element is based on binary stochastic arithmetic to perform signal processing operations on the focal plane VLSI circuit. A 96 × 64 CMOS image sensor is fabricated using 0.5μm CMOS technology and achieves 29 × 29μm pixel size at 15% fill factor.

AB - A chip architecture that integrates an optical sensor and a pixel level processing element based on binary stochastic arithmetic is proposed. The optical sensor is formed by an array of fully connected pixels, and each pixel contains a sensing element and a Pulse Frequency Modulator (PFM) converting the incident light to bit streams of identical pulses. The processing element is based on binary stochastic arithmetic to perform signal processing operations on the focal plane VLSI circuit. A 96 × 64 CMOS image sensor is fabricated using 0.5μm CMOS technology and achieves 29 × 29μm pixel size at 15% fill factor.

UR - http://www.scopus.com/inward/record.url?scp=0038757578&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0038757578

SN - 0271-4310

VL - 4

SP - IV772-IV775

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

T2 - Proceedings of the 2003 IEEE International Symposium on Circuits and Systems

Y2 - 25 May 2003 through 28 May 2003

ER -

A 96 × 64 Intelligent digital pixel array with extended binary stochastic arithmetic

Abstract

Other files and links

Fingerprint

Cite this