TY - GEN
T1 - A background subtraction based column-parallel analog-to-information converter for motion-triggered vision sensor
AU - Zhong, Xiaopeng
AU - Zhang, Bo
AU - Bermak, Amine
N1 - Publisher Copyright:
© 2016 IEEE.
PY - 2016/7/29
Y1 - 2016/7/29
N2 - An analog-to-information converter (AIC) enables information quantization instead of signal quantization, which can reduce both quantization efforts and data bandwidth. Therefore, an AIC will relax data processing and transmission burden and improve overall power efficiency, making it attractive for wireless vision sensor networks. In this paper, we propose a background subtraction based column-parallel AIC for motion-triggered vision sensors. It features low-power and robust background subtraction for motion extraction as well as efficient information quantization. The AIC is implemented by integrating background subtraction with a successive-approximation-register and single-lope (SAR-SS) hybrid ADC using a new architecture. Targeting at scene interpretation applications, 6-bit background and 8-bit foreground are adopted. Simulation results show that vision data bandwidth and ADC power are reduced by 85.23% and 95.88% respectively when full-bit-depth motion images are required. The bandwidth reduction and the ADC power reduction can be further improved to 87.50% and 98.48% respectively if only binary motion images are needed.
AB - An analog-to-information converter (AIC) enables information quantization instead of signal quantization, which can reduce both quantization efforts and data bandwidth. Therefore, an AIC will relax data processing and transmission burden and improve overall power efficiency, making it attractive for wireless vision sensor networks. In this paper, we propose a background subtraction based column-parallel AIC for motion-triggered vision sensors. It features low-power and robust background subtraction for motion extraction as well as efficient information quantization. The AIC is implemented by integrating background subtraction with a successive-approximation-register and single-lope (SAR-SS) hybrid ADC using a new architecture. Targeting at scene interpretation applications, 6-bit background and 8-bit foreground are adopted. Simulation results show that vision data bandwidth and ADC power are reduced by 85.23% and 95.88% respectively when full-bit-depth motion images are required. The bandwidth reduction and the ADC power reduction can be further improved to 87.50% and 98.48% respectively if only binary motion images are needed.
UR - http://www.scopus.com/inward/record.url?scp=84983427637&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2016.7527518
DO - 10.1109/ISCAS.2016.7527518
M3 - Conference contribution
AN - SCOPUS:84983427637
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 1426
EP - 1429
BT - ISCAS 2016 - IEEE International Symposium on Circuits and Systems
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016
Y2 - 22 May 2016 through 25 May 2016
ER -