TY - GEN
T1 - A chopper instrumentation amplifier with amplifier slicing technique for offset reduction
AU - Lin, Tsz Ngai
AU - Wang, Bo
AU - Belhaouari, Samir Brahim
AU - Bermak, Amine
N1 - Publisher Copyright:
© 2020 IEEE
PY - 2020
Y1 - 2020
N2 - This paper presents a chopper instrumentation amplifier design that employs a proposed amplifier slicing technique for offset reduction. In this scheme, the core amplifier is split into multiple identical slices. During operation, the offset polarity of these slices is firstly determined by employing the second-stage of the amplifier as a static comparator. Next, by using the polarity information, the amplifier slices are regrouped to achieve statistical offset suppression. A mathematical model is developed in this paper to estimate the effectiveness of this reduction scheme. The sliced amplifier structure also enables a scalable noise and bandwidth without adding extra analog components. Simulation results show that the proposed reduction scheme achieves a > 40 dB offset suppression and a noise efficiency factor (NEF) of 2.2. The circuit is implemented in a 0.18 µm standard CMOS technology for proof of concept and consumes 0.4 µA to 1 µA current from a 1.2 V supply to reach a noise level from 90 nV/√Hz to 31.8 nV/√Hz, respectively.
AB - This paper presents a chopper instrumentation amplifier design that employs a proposed amplifier slicing technique for offset reduction. In this scheme, the core amplifier is split into multiple identical slices. During operation, the offset polarity of these slices is firstly determined by employing the second-stage of the amplifier as a static comparator. Next, by using the polarity information, the amplifier slices are regrouped to achieve statistical offset suppression. A mathematical model is developed in this paper to estimate the effectiveness of this reduction scheme. The sliced amplifier structure also enables a scalable noise and bandwidth without adding extra analog components. Simulation results show that the proposed reduction scheme achieves a > 40 dB offset suppression and a noise efficiency factor (NEF) of 2.2. The circuit is implemented in a 0.18 µm standard CMOS technology for proof of concept and consumes 0.4 µA to 1 µA current from a 1.2 V supply to reach a noise level from 90 nV/√Hz to 31.8 nV/√Hz, respectively.
UR - http://www.scopus.com/inward/record.url?scp=85109308225&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:85109308225
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
BT - 2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020
Y2 - 10 October 2020 through 21 October 2020
ER -