A column-parallel inverter-based cyclic ADC for CMOS image sensor with capacitance and clock scaling

This paper presents a low-power column-parallel inverter-based cyclic analog-to-digital converter (ADC) for CMOS image sensor readout circuit. By partially floating the capacitors inside the multiply digital-analog-converter during the least significant bit (LSB) quantization, the amplifier load capacitance could be significantly scaled down, which allows much higher settling speed and shorter cycle period. Since the signal-to-noise ratio for LSB cycle is relaxed due to the residual amplification, the proposed capacitance scaling only contributes ignorable input-referred quantization noise. Using the proposed techniques, a cyclic ADC can operate under 50% power consumption without suffering conversion rate, noise performance, and linearity. A 12-b quantization resolution test chip is fabricated using the TSMC 0.18-μm technology with 110 column-parallel ADC channels and 10.08-μm × 750-μm column pitch. The 3.5/-2 LSBs integral nonlinearity and 10.1-b effective-number-of-bit are measured under 2-μs sampling rate with 120-μW power consumption per channel.