A compact CMOS face detection architecture based on Shunting Inhibitory Convolutional Neural Networks

Xiaoxiao Zhang; Amine Bennak; Farid Boussaid; A. Bouzerdoum

doi:10.1109/DELTA.2008.66

A compact CMOS face detection architecture based on Shunting Inhibitory Convolutional Neural Networks

Xiaoxiao Zhang^*, Amine Bennak, Farid Boussaid, A. Bouzerdoum

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

In this paper, we present a compact, low cost, real-time CMOS hardware architecture for face detection. The proposed architecture is based on a VLSI-friendly implementation of Shunting Inhibitory Convolutional Neural Networks (SICoNN). Reported experimental results show that the proposed architecture can detect faces with 93% detection accuracy at 5% false alarm rate. A VLSI Systolic architecture was considered to further optimize the design in terms of execution speed, power dissipation and area. Potential applications of the proposed face detection hardware include consumer electronics, security, monitoring and head-counting.

Original language	English
Title of host publication	Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008
Pages	374-377
Number of pages	4
DOIs	https://doi.org/10.1109/DELTA.2008.66
Publication status	Published - 2008
Externally published	Yes
Event	4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008 - Hong Kong, SAR, Hong Kong Duration: 23 Jan 2008 → 25 Jan 2008

Publication series

Name	Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008

Conference

Conference	4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008
Country/Territory	Hong Kong
City	Hong Kong, SAR
Period	23/01/08 → 25/01/08

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10.1109/DELTA.2008.66

Cite this

Zhang, X., Bennak, A., Boussaid, F., & Bouzerdoum, A. (2008). A compact CMOS face detection architecture based on Shunting Inhibitory Convolutional Neural Networks. In Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008 (pp. 374-377). Article 4459574 (Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008). https://doi.org/10.1109/DELTA.2008.66

Zhang, Xiaoxiao ; Bennak, Amine ; Boussaid, Farid et al. / A compact CMOS face detection architecture based on Shunting Inhibitory Convolutional Neural Networks. Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008. 2008. pp. 374-377 (Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008).

@inproceedings{eab1a4f1bfcf4f1cba0976c86708c2f5,

title = "A compact CMOS face detection architecture based on Shunting Inhibitory Convolutional Neural Networks",

abstract = "In this paper, we present a compact, low cost, real-time CMOS hardware architecture for face detection. The proposed architecture is based on a VLSI-friendly implementation of Shunting Inhibitory Convolutional Neural Networks (SICoNN). Reported experimental results show that the proposed architecture can detect faces with 93% detection accuracy at 5% false alarm rate. A VLSI Systolic architecture was considered to further optimize the design in terms of execution speed, power dissipation and area. Potential applications of the proposed face detection hardware include consumer electronics, security, monitoring and head-counting.",

author = "Xiaoxiao Zhang and Amine Bennak and Farid Boussaid and A. Bouzerdoum",

year = "2008",

doi = "10.1109/DELTA.2008.66",

language = "English",

isbn = "0769531105",

series = "Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008",

pages = "374--377",

booktitle = "Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008",

note = "4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008 ; Conference date: 23-01-2008 Through 25-01-2008",

}

Zhang, X, Bennak, A, Boussaid, F & Bouzerdoum, A 2008, A compact CMOS face detection architecture based on Shunting Inhibitory Convolutional Neural Networks. in Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008., 4459574, Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, pp. 374-377, 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, Hong Kong, SAR, Hong Kong, 23/01/08. https://doi.org/10.1109/DELTA.2008.66

A compact CMOS face detection architecture based on Shunting Inhibitory Convolutional Neural Networks. / Zhang, Xiaoxiao; Bennak, Amine; Boussaid, Farid et al.
Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008. 2008. p. 374-377 4459574 (Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Boussaid, Farid

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N2 - In this paper, we present a compact, low cost, real-time CMOS hardware architecture for face detection. The proposed architecture is based on a VLSI-friendly implementation of Shunting Inhibitory Convolutional Neural Networks (SICoNN). Reported experimental results show that the proposed architecture can detect faces with 93% detection accuracy at 5% false alarm rate. A VLSI Systolic architecture was considered to further optimize the design in terms of execution speed, power dissipation and area. Potential applications of the proposed face detection hardware include consumer electronics, security, monitoring and head-counting.

AB - In this paper, we present a compact, low cost, real-time CMOS hardware architecture for face detection. The proposed architecture is based on a VLSI-friendly implementation of Shunting Inhibitory Convolutional Neural Networks (SICoNN). Reported experimental results show that the proposed architecture can detect faces with 93% detection accuracy at 5% false alarm rate. A VLSI Systolic architecture was considered to further optimize the design in terms of execution speed, power dissipation and area. Potential applications of the proposed face detection hardware include consumer electronics, security, monitoring and head-counting.

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M3 - Conference contribution

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BT - Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008

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Zhang X, Bennak A, Boussaid F, Bouzerdoum A. A compact CMOS face detection architecture based on Shunting Inhibitory Convolutional Neural Networks. In Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008. 2008. p. 374-377. 4459574. (Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008). doi: 10.1109/DELTA.2008.66

A compact CMOS face detection architecture based on Shunting Inhibitory Convolutional Neural Networks

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