A compact multi-chip-module implementation of a multi-precision neural network classifier

Amine Bermak; Dominique Martinez

doi:10.1109/ISCAS.2001.921294

A compact multi-chip-module implementation of a multi-precision neural network classifier

Amine Bermak, Dominique Martinez

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Citations (Scopus)

Abstract

This paper describes a novel MCM digital implementation of a reconfigurable multi-precision neural network classifier. The design is based on a scalable systolic architecture with a user defined topology and arithmetic precision of the neural network. Indeed, the MCM integrates 64/32/16 neurons with a corresponding accuracy of 4/8/16-bits. A prototype has been designed and successfully tested in CMOS 0.7 μm technology.

Original language	English
Title of host publication	ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
Pages	249-252
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2001.921294
Publication status	Published - 2001
Externally published	Yes
Event	2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001 - Sydney, NSW, Australia Duration: 6 May 2001 → 9 May 2001

Publication series

Name	ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
Volume	3

Conference

Conference	2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001
Country/Territory	Australia
City	Sydney, NSW
Period	6/05/01 → 9/05/01

Access to Document

10.1109/ISCAS.2001.921294

Cite this

Bermak, A., & Martinez, D. (2001). A compact multi-chip-module implementation of a multi-precision neural network classifier. In ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings (pp. 249-252). Article 921294 (ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings; Vol. 3). https://doi.org/10.1109/ISCAS.2001.921294

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title = "A compact multi-chip-module implementation of a multi-precision neural network classifier",

abstract = "This paper describes a novel MCM digital implementation of a reconfigurable multi-precision neural network classifier. The design is based on a scalable systolic architecture with a user defined topology and arithmetic precision of the neural network. Indeed, the MCM integrates 64/32/16 neurons with a corresponding accuracy of 4/8/16-bits. A prototype has been designed and successfully tested in CMOS 0.7 μm technology.",

author = "Amine Bermak and Dominique Martinez",

year = "2001",

doi = "10.1109/ISCAS.2001.921294",

language = "English",

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series = "ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings",

pages = "249--252",

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note = "2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001 ; Conference date: 06-05-2001 Through 09-05-2001",

}

Bermak, A & Martinez, D 2001, A compact multi-chip-module implementation of a multi-precision neural network classifier. in ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings., 921294, ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings, vol. 3, pp. 249-252, 2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001, Sydney, NSW, Australia, 6/05/01. https://doi.org/10.1109/ISCAS.2001.921294

A compact multi-chip-module implementation of a multi-precision neural network classifier. / Bermak, Amine; Martinez, Dominique.
ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings. 2001. p. 249-252 921294 (ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings; Vol. 3).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - This paper describes a novel MCM digital implementation of a reconfigurable multi-precision neural network classifier. The design is based on a scalable systolic architecture with a user defined topology and arithmetic precision of the neural network. Indeed, the MCM integrates 64/32/16 neurons with a corresponding accuracy of 4/8/16-bits. A prototype has been designed and successfully tested in CMOS 0.7 μm technology.

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A compact multi-chip-module implementation of a multi-precision neural network classifier

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