TY - GEN
T1 - A Cryo-CMOS 4.57GHz Dual-Qubit Homodyne Reflectometer Array with High Q Degenerate Parametric Amplifier Through Dynamic Mode Coupling
AU - Geng, Yujie
AU - Lin, Haichuan
AU - Wang, Bo
AU - Wang, Cheng
N1 - Publisher Copyright:
© 2023 IEEE.
PY - 2023
Y1 - 2023
N2 - Error-corrected quantum computing does not only require large-scale (106-109) physical Qubit arrays but also relies on high-fidelity, scalable quantum-to-classic interface electronics. Quantum control and readout systems based on cryogenic CMOS integrated circuits mitigate the error of Qubit manipulation, reduce the cabling complexity, and facilitate the quantum feedback, which pave the way towards practical quantum error correction (QEC) and logic quantum gates. RF reflectometry is widely adopted for qubit states readout. Reflectometry conducts Qubit states discrimination (collapsed to '0' or '1') by detecting the resonant frequency through RF reflection of a high-Q LC tank associated with the sensor Qubit (Fig. 1). The quantum states are encoded in either the amplitude or the phase of the reflected RF signal. Compared with its DC counterpart, the reflectometry achieves unprecedented charge sensitivity, reduces the integration time, and avoids long-term drifting. However, conventional heterodyne reflectometer schemes [1][4][5] adopt sophisticated up/down mixers, ADC, DAC, and PLL for the Qubit excitation and down-mixing, respectively. They suffer from poor TX-RX isolation, inter-modulation, and high DC power, which deteriorate the scalability and readout fidelity. To address these challenges, a highly scalable dual-Qubit homodyne reflectometer array is proposed in this paper. It drives the LC tank by a single PLL and detects the reflection by a high-gain degenerate parametric amplifier (DPA). Along with fast modulation and lock-in detection, it mitigates the interference, complex cabling, and high DC power of conventional heterodyne reflectometers.
AB - Error-corrected quantum computing does not only require large-scale (106-109) physical Qubit arrays but also relies on high-fidelity, scalable quantum-to-classic interface electronics. Quantum control and readout systems based on cryogenic CMOS integrated circuits mitigate the error of Qubit manipulation, reduce the cabling complexity, and facilitate the quantum feedback, which pave the way towards practical quantum error correction (QEC) and logic quantum gates. RF reflectometry is widely adopted for qubit states readout. Reflectometry conducts Qubit states discrimination (collapsed to '0' or '1') by detecting the resonant frequency through RF reflection of a high-Q LC tank associated with the sensor Qubit (Fig. 1). The quantum states are encoded in either the amplitude or the phase of the reflected RF signal. Compared with its DC counterpart, the reflectometry achieves unprecedented charge sensitivity, reduces the integration time, and avoids long-term drifting. However, conventional heterodyne reflectometer schemes [1][4][5] adopt sophisticated up/down mixers, ADC, DAC, and PLL for the Qubit excitation and down-mixing, respectively. They suffer from poor TX-RX isolation, inter-modulation, and high DC power, which deteriorate the scalability and readout fidelity. To address these challenges, a highly scalable dual-Qubit homodyne reflectometer array is proposed in this paper. It drives the LC tank by a single PLL and detects the reflection by a high-gain degenerate parametric amplifier (DPA). Along with fast modulation and lock-in detection, it mitigates the interference, complex cabling, and high DC power of conventional heterodyne reflectometers.
UR - http://www.scopus.com/inward/record.url?scp=85181543343&partnerID=8YFLogxK
U2 - 10.1109/A-SSCC58667.2023.10347990
DO - 10.1109/A-SSCC58667.2023.10347990
M3 - Conference contribution
AN - SCOPUS:85181543343
T3 - 2023 IEEE Asian Solid-State Circuits Conference, A-SSCC 2023
BT - 2023 IEEE Asian Solid-State Circuits Conference, A-SSCC 2023
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 19th IEEE Asian Solid-State Circuits Conference, A-SSCC 2023
Y2 - 5 November 2023 through 8 November 2023
ER -