A digital CMOS imager with pixel level analog-to-digital converter and reconfigurable SRAM/counter

Yat Fong Yung; Amine Bermak

A digital CMOS imager with pixel level analog-to-digital converter and reconfigurable SRAM/counter

Yat Fong Yung^*, Amine Bermak

^*Corresponding author for this work

Hong Kong University of Science and Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Citation (Scopus)

Abstract

In this paper a CMOS image sensor with on-pixel analog-to-digital convener based on PWM scheme is proposed. The digital pixel sensor includes a novel digital circuit which allows to configure the internal 8-bit memory as a 4-bit counter/memory, so as to reduce the data bit lines routed to each pixel from 8-bit to 4-bit. Hence the total parasitic capacitance as well as power consumption associated with the switching activities of the global data bus lines are reduced. Besides 8-bit precision, the imager can also be configured to 4-bit precision for low resolution applications, which has the advantage of increasing frame rate and decreasing overall power consumption. A prototype chip was realized in Alcatel 0.35μm CMOS technology. Each pixel occupies an area of 46μm × 48μm with a fill-factor of 14%.

Original language	English
Title of host publication	Proceedings - 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2004
Editors	W. Badawy, Y. Ismail
Pages	33-36
Number of pages	4
Publication status	Published - 2004
Externally published	Yes
Event	Proceedings - 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2004 - Banff, Alta, Canada Duration: 19 Jul 2004 → 21 Jul 2004

Publication series

Name	Proceedings - 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2004

Conference

Conference	Proceedings - 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2004
Country/Territory	Canada
City	Banff, Alta
Period	19/07/04 → 21/07/04

Cite this

Yung, Y. F., & Bermak, A. (2004). A digital CMOS imager with pixel level analog-to-digital converter and reconfigurable SRAM/counter. In W. Badawy, & Y. Ismail (Eds.), Proceedings - 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2004 (pp. 33-36). (Proceedings - 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2004).

Yung, Yat Fong ; Bermak, Amine. / A digital CMOS imager with pixel level analog-to-digital converter and reconfigurable SRAM/counter. Proceedings - 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2004. editor / W. Badawy ; Y. Ismail. 2004. pp. 33-36 (Proceedings - 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2004).

@inproceedings{d618dd0182874f549b6e84e8250536d6,

title = "A digital CMOS imager with pixel level analog-to-digital converter and reconfigurable SRAM/counter",

abstract = "In this paper a CMOS image sensor with on-pixel analog-to-digital convener based on PWM scheme is proposed. The digital pixel sensor includes a novel digital circuit which allows to configure the internal 8-bit memory as a 4-bit counter/memory, so as to reduce the data bit lines routed to each pixel from 8-bit to 4-bit. Hence the total parasitic capacitance as well as power consumption associated with the switching activities of the global data bus lines are reduced. Besides 8-bit precision, the imager can also be configured to 4-bit precision for low resolution applications, which has the advantage of increasing frame rate and decreasing overall power consumption. A prototype chip was realized in Alcatel 0.35μm CMOS technology. Each pixel occupies an area of 46μm × 48μm with a fill-factor of 14%.",

author = "Yung, {Yat Fong} and Amine Bermak",

year = "2004",

language = "English",

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series = "Proceedings - 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2004",

pages = "33--36",

editor = "W. Badawy and Y. Ismail",

booktitle = "Proceedings - 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2004",

note = "Proceedings - 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2004 ; Conference date: 19-07-2004 Through 21-07-2004",

}

Yung, YF & Bermak, A 2004, A digital CMOS imager with pixel level analog-to-digital converter and reconfigurable SRAM/counter. in W Badawy & Y Ismail (eds), Proceedings - 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2004. Proceedings - 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2004, pp. 33-36, Proceedings - 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2004, Banff, Alta, Canada, 19/07/04.

A digital CMOS imager with pixel level analog-to-digital converter and reconfigurable SRAM/counter. / Yung, Yat Fong; Bermak, Amine.
Proceedings - 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2004. ed. / W. Badawy; Y. Ismail. 2004. p. 33-36 (Proceedings - 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2004).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A digital CMOS imager with pixel level analog-to-digital converter and reconfigurable SRAM/counter

AU - Yung, Yat Fong

AU - Bermak, Amine

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N2 - In this paper a CMOS image sensor with on-pixel analog-to-digital convener based on PWM scheme is proposed. The digital pixel sensor includes a novel digital circuit which allows to configure the internal 8-bit memory as a 4-bit counter/memory, so as to reduce the data bit lines routed to each pixel from 8-bit to 4-bit. Hence the total parasitic capacitance as well as power consumption associated with the switching activities of the global data bus lines are reduced. Besides 8-bit precision, the imager can also be configured to 4-bit precision for low resolution applications, which has the advantage of increasing frame rate and decreasing overall power consumption. A prototype chip was realized in Alcatel 0.35μm CMOS technology. Each pixel occupies an area of 46μm × 48μm with a fill-factor of 14%.

AB - In this paper a CMOS image sensor with on-pixel analog-to-digital convener based on PWM scheme is proposed. The digital pixel sensor includes a novel digital circuit which allows to configure the internal 8-bit memory as a 4-bit counter/memory, so as to reduce the data bit lines routed to each pixel from 8-bit to 4-bit. Hence the total parasitic capacitance as well as power consumption associated with the switching activities of the global data bus lines are reduced. Besides 8-bit precision, the imager can also be configured to 4-bit precision for low resolution applications, which has the advantage of increasing frame rate and decreasing overall power consumption. A prototype chip was realized in Alcatel 0.35μm CMOS technology. Each pixel occupies an area of 46μm × 48μm with a fill-factor of 14%.

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M3 - Conference contribution

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BT - Proceedings - 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2004

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Yung YF, Bermak A. A digital CMOS imager with pixel level analog-to-digital converter and reconfigurable SRAM/counter. In Badawy W, Ismail Y, editors, Proceedings - 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2004. 2004. p. 33-36. (Proceedings - 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2004).

A digital CMOS imager with pixel level analog-to-digital converter and reconfigurable SRAM/counter

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