A ladder transistor-clamped multilevel inverter with high-voltage variation

Eshet T. Wodajo, Malik Elbuluk, Seungdeog Choi, Haitham Abu Rub

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Citations (Scopus)

Abstract

In this paper, a new ladder transistor clamped multilevel inverter topology is proposed with the aim of reducing the number of transistor, while maintaining the bidirectionalcontrolled current flow capability of the transistor-clamped topologies. The basic structural features of the topology are presented along with their operational purpose. The merits of the new topology with respect to other topologies in the low-voltage and high-voltage operations are discussed. In addition, the semimodular characteristics of the structure are discussed in regard to the scalability of the topology. Finally, the validity of the structure is demonstrated using simulation results for different voltage variations of the topology and a three-phase structure.

Original languageEnglish
Title of host publication2017 IEEE Energy Conversion Congress and Exposition, ECCE 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages5679-5684
Number of pages6
ISBN (Electronic)9781509029983
DOIs
Publication statusPublished - 3 Nov 2017
Externally publishedYes
Event9th Annual IEEE Energy Conversion Congress and Exposition, ECCE 2017 - Cincinnati, United States
Duration: 1 Oct 20175 Oct 2017

Publication series

Name2017 IEEE Energy Conversion Congress and Exposition, ECCE 2017
Volume2017-January

Conference

Conference9th Annual IEEE Energy Conversion Congress and Exposition, ECCE 2017
Country/TerritoryUnited States
CityCincinnati
Period1/10/175/10/17

Keywords

  • High Voltage.
  • Ladder Topology
  • Multilevel Inverter
  • Scalability
  • Transistor-Clamped

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