TY - JOUR
T1 - A Low-Power Column-Parallel ΣΔ ADC with Shared OTAs and Single-Bit-BWI Decimation Filter for CMOS Image Sensor
AU - Wang, Zhongjie
AU - Ma, Qiyun
AU - Yang, Tongbei
AU - Lin, Zhi
AU - Bermak, Amine
AU - Tang, Fang
N1 - Publisher Copyright:
© 1963-2012 IEEE.
PY - 2022/6/1
Y1 - 2022/6/1
N2 - This article presents a low-power column-parallel analog-To-digital converter (ADC) with shared operational transconductance amplifiers (OTAs) for CMOS image sensors (CISs). Through the proposed time division multiplexing of OTAs, the power consumption of the modulator achieves a reduction of about 40%. The proposed structure alleviates the layout requirement of OTAs, enabling implementation of a high-resolution low-power image sensor in advanced CMOS technology nodes. As the coupled noise introduced by the proposed column-shared scheme is suppressed to a lower level than the inherent crosstalk of adjacent pixels, the proposed structure only contributes a negligible inter-column coupled noise from the ADCs. Moreover, a compact digital decimation filter with a single-bit-bit-wise-inversion (BWI) topology is also proposed, which can reduce chip area significantly. The prototype sensor is fabricated in a 40-nm standard CMOS technology with 256 × 256 pixel array and 256 proposed column-parallel ADCs. Each ADC occupies a core area of 4.5 {m}310 {m} , while consuming a power of 58.8 {W}. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are +0.49/-0.65 LSB and +5.1/-4.8 LSB, respectively. Measurement results show a dynamic range of 79.9 dB and an effective-number-of-bit (ENOB) of 11.4 bit. This work achieves a figure of merit (FOM) of 97.2 fJ/step.
AB - This article presents a low-power column-parallel analog-To-digital converter (ADC) with shared operational transconductance amplifiers (OTAs) for CMOS image sensors (CISs). Through the proposed time division multiplexing of OTAs, the power consumption of the modulator achieves a reduction of about 40%. The proposed structure alleviates the layout requirement of OTAs, enabling implementation of a high-resolution low-power image sensor in advanced CMOS technology nodes. As the coupled noise introduced by the proposed column-shared scheme is suppressed to a lower level than the inherent crosstalk of adjacent pixels, the proposed structure only contributes a negligible inter-column coupled noise from the ADCs. Moreover, a compact digital decimation filter with a single-bit-bit-wise-inversion (BWI) topology is also proposed, which can reduce chip area significantly. The prototype sensor is fabricated in a 40-nm standard CMOS technology with 256 × 256 pixel array and 256 proposed column-parallel ADCs. Each ADC occupies a core area of 4.5 {m}310 {m} , while consuming a power of 58.8 {W}. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are +0.49/-0.65 LSB and +5.1/-4.8 LSB, respectively. Measurement results show a dynamic range of 79.9 dB and an effective-number-of-bit (ENOB) of 11.4 bit. This work achieves a figure of merit (FOM) of 97.2 fJ/step.
KW - CMOS image sensor (CIS)
KW - analog-To-digital converter (ADC)
KW - column-parallel readout circuit
KW - digital decimation filter
KW - low power
KW - shared operational transconductance amplifier (OTA)
UR - http://www.scopus.com/inward/record.url?scp=85130505493&partnerID=8YFLogxK
U2 - 10.1109/TED.2022.3171742
DO - 10.1109/TED.2022.3171742
M3 - Article
AN - SCOPUS:85130505493
SN - 0018-9383
VL - 69
SP - 2979
EP - 2985
JO - IEEE Transactions on Electron Devices
JF - IEEE Transactions on Electron Devices
IS - 6
ER -