A low-power dynamic comparator with digital calibration for reduced offset mismatch

This paper describes a fully dynamic analog comparator with digital calibration for very low offset error. In this work, we propose an off-line calibration scheme where the offset error is quantized by successive approximation. During run-time, the offset is cancelled by a digital-to-analog converter (DAC). We further improve the robustness of this cancellation by using a redundant cell to compensate for any internal mismatch within the DAC. Simulation in 0.18 um CMOS technology shows that our scheme can reduce the offset error to less than 0.86 mV _rms under 1.8 V supply. The comparator consumes 1.4 pJ, and the clock to data delay is 3.5 ns.