A New read-out circuit for low power current and voltage mediated integrating CMOS imager

This paper proposes a new read-out strategy for integrating type of CMOS imagers. The approach uses a single counter and two address decoders for generating both the reset and the selection signals needed for an integrating image sensor array together with the electronic shutter functionality. In contrast to the traditional integrating read-out approaches, our reset and read-out phases are carried out simultaneously. The array is scanned with only a single pixel selected for reset and another pixel selected for read-out. This approach results in significant benefits such as silicon area savings, low power operation, simple electronic shutter as well as equal and programmable integration time for all pixels within the array. The functionality of the proposed approach and its VLSI implementation is illustrated using the example of the current-mediated image sensor proposed by McIlrath et al. in [1].