Abstract
This paper presents a novel recursive algorithm for generating higher order m-dimensional (m-D) convolution by combining the computation of 3m identical lower order (smaller size) convolution computations, and its implementation in parallel VLSI networks. The resulting VLSI architectures have very simple modular structure, highly regular topology, and use simple arithmetic units. Additionally, the proposed architectures have very small depth and contain only a single stage of multipliers, while all other stages contain adders only.
Original language | English |
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Pages (from-to) | 652-654 |
Number of pages | 3 |
Journal | IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing |
Volume | 46 |
Issue number | 5 |
DOIs | |
Publication status | Published - 1999 |
Externally published | Yes |
Keywords
- Multidimensional convolution
- Parallel vlsi architectures
- Permutation matrices
- Recursive architectures
- Tensor product