TY - GEN
T1 - A power minimized 74 fJ/conversion-step 88.6 dB SNR incremental ΣΔ ADC with an asynchronous SAR quantizer
AU - Mohamad, Saqib
AU - Chao, Wu
AU - Yuan, Jie
AU - Bermak, Amine
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/9/25
Y1 - 2017/9/25
N2 - Incremental analog to digital converters (lADCs) are aimed at converting low frequency signals with high accuracy. However the use of high oversampling ratios (OSR) usually decreases the conversion speed making them energy inefficient. The first integrator also consumes a lot of power due to high settling requirements, if a single bit quantizer is used. This paper introduces a two step feedforward IADC using an asynchronous Successive Approximation Register (SAR) ADC as a multi-bit quantizer. The same SAR ADC is then used to convert the residue of the incremental conversion. The extended counting enables high conversion speed and the use of a multibit quantizer reduces settling requirements for the first integrator. As a result, high power efficiency is achieved. The ADC achieves a peak SNR of 88.6 dB within a Nyquist bandwidth of 2.5 kHz, with a power consumption of only 8.44 μW. The measured Waiden and Schreier FoMs are 74 fj/conv.-step and 173.3 dB, respectively.
AB - Incremental analog to digital converters (lADCs) are aimed at converting low frequency signals with high accuracy. However the use of high oversampling ratios (OSR) usually decreases the conversion speed making them energy inefficient. The first integrator also consumes a lot of power due to high settling requirements, if a single bit quantizer is used. This paper introduces a two step feedforward IADC using an asynchronous Successive Approximation Register (SAR) ADC as a multi-bit quantizer. The same SAR ADC is then used to convert the residue of the incremental conversion. The extended counting enables high conversion speed and the use of a multibit quantizer reduces settling requirements for the first integrator. As a result, high power efficiency is achieved. The ADC achieves a peak SNR of 88.6 dB within a Nyquist bandwidth of 2.5 kHz, with a power consumption of only 8.44 μW. The measured Waiden and Schreier FoMs are 74 fj/conv.-step and 173.3 dB, respectively.
UR - http://www.scopus.com/inward/record.url?scp=85032690998&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2017.8050248
DO - 10.1109/ISCAS.2017.8050248
M3 - Conference contribution
AN - SCOPUS:85032690998
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
BT - IEEE International Symposium on Circuits and Systems
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 50th IEEE International Symposium on Circuits and Systems, ISCAS 2017
Y2 - 28 May 2017 through 31 May 2017
ER -