A scalable low power imager architecture for compound-eye vision sensors

Farid Boussaid; Chen Shoushun; Amine Bermak

doi:10.1109/IWSOC.2005.26

A scalable low power imager architecture for compound-eye vision sensors

Farid Boussaid^*, Chen Shoushun, Amine Bermak

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Citation (Scopus)

Abstract

In this paper, we propose a scalable low power imager architecture for compound-eye vision sensors. The proposed hardware architecture is based on a time domain data representation as well as a biologically inspired read-out strategy using Address-Event-Representation (AER). The proposed AER approach to compound-eye Imaging enables low power operation (lOnA/pixel), efficient read-out, improved signal-to-noise ratio together with wide dynamic range. Moreover, the proposed AER-based VLSI architecture is scalable and well suited to the next generation of deep submicron silicon processes owing to decreased supply voltage, process variability and Increased noise levels.

Original language	English
Title of host publication	Proceedings - Fifth International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2005
Pages	203-206
Number of pages	4
DOIs	https://doi.org/10.1109/IWSOC.2005.26
Publication status	Published - 2005
Externally published	Yes
Event	Fifth International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2005 - Banff, Alta., Canada Duration: 20 Jul 2005 → 24 Jul 2005

Publication series

Name	Proceedings - Fifth International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2005
Volume	2005

Conference

Conference	Fifth International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2005
Country/Territory	Canada
City	Banff, Alta.
Period	20/07/05 → 24/07/05

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10.1109/IWSOC.2005.26

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Boussaid, F., Shoushun, C., & Bermak, A. (2005). A scalable low power imager architecture for compound-eye vision sensors. In Proceedings - Fifth International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2005 (pp. 203-206). Article 1530942 (Proceedings - Fifth International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2005; Vol. 2005). https://doi.org/10.1109/IWSOC.2005.26

@inproceedings{ef9033a4cc9f42c4a39432b4c3989001,

title = "A scalable low power imager architecture for compound-eye vision sensors",

abstract = "In this paper, we propose a scalable low power imager architecture for compound-eye vision sensors. The proposed hardware architecture is based on a time domain data representation as well as a biologically inspired read-out strategy using Address-Event-Representation (AER). The proposed AER approach to compound-eye Imaging enables low power operation (lOnA/pixel), efficient read-out, improved signal-to-noise ratio together with wide dynamic range. Moreover, the proposed AER-based VLSI architecture is scalable and well suited to the next generation of deep submicron silicon processes owing to decreased supply voltage, process variability and Increased noise levels.",

author = "Farid Boussaid and Chen Shoushun and Amine Bermak",

year = "2005",

doi = "10.1109/IWSOC.2005.26",

language = "English",

isbn = "0769524036",

series = "Proceedings - Fifth International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2005",

pages = "203--206",

booktitle = "Proceedings - Fifth International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2005",

note = "Fifth International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2005 ; Conference date: 20-07-2005 Through 24-07-2005",

}

Boussaid, F, Shoushun, C & Bermak, A 2005, A scalable low power imager architecture for compound-eye vision sensors. in Proceedings - Fifth International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2005., 1530942, Proceedings - Fifth International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2005, vol. 2005, pp. 203-206, Fifth International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2005, Banff, Alta., Canada, 20/07/05. https://doi.org/10.1109/IWSOC.2005.26

A scalable low power imager architecture for compound-eye vision sensors. / Boussaid, Farid; Shoushun, Chen; Bermak, Amine.
Proceedings - Fifth International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2005. 2005. p. 203-206 1530942 (Proceedings - Fifth International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2005; Vol. 2005).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Shoushun, Chen

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AB - In this paper, we propose a scalable low power imager architecture for compound-eye vision sensors. The proposed hardware architecture is based on a time domain data representation as well as a biologically inspired read-out strategy using Address-Event-Representation (AER). The proposed AER approach to compound-eye Imaging enables low power operation (lOnA/pixel), efficient read-out, improved signal-to-noise ratio together with wide dynamic range. Moreover, the proposed AER-based VLSI architecture is scalable and well suited to the next generation of deep submicron silicon processes owing to decreased supply voltage, process variability and Increased noise levels.

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M3 - Conference contribution

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SN - 9780769524030

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BT - Proceedings - Fifth International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2005

T2 - Fifth International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2005

Y2 - 20 July 2005 through 24 July 2005

ER -

A scalable low power imager architecture for compound-eye vision sensors

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