Accelerating Performance of Bilinear Map Cryptography using FPGA

Bilinear maps are used as an essential cryptographic building block in many of the advanced encryption algorithms today, such as searchable encryption, identity-based encryption, group signatures, etc. Numerous data and application privacy techniques make use of such primitives. However, the performance overhead of bilinear map encryption, and in particular that of the pairing operation, which is the predominant operation on bilinear maps, is still quite high. In this paper, we investigate in-depth the sequence of steps required to compute bilinear map pairings, and we identify the performance footprint of each step. We devise an implementation based on FPGA which reduces the overhead of bilinear pairings, in terms of both execution time and resource utilization (i.e., lookup tables and flip-flop units required). Our extensive performance evaluation shows that the proposed approach significantly outperforms benchmarks, and represents an important step towards the wide-scale deployment of bilinear map-based encryption protocol for large-scale applications.