TY - JOUR
T1 - An area-efficient column-parallel digital decimation filter with Pre-BWI Topology for CMOS Image Sensor
AU - Tang, Fang
AU - Wang, Zhongjie
AU - Xia, Yingjun
AU - Liu, Fan
AU - Zhou, Xichuan
AU - Hu, Shengdong
AU - Lin, Zhi
AU - Bermak, Amine
N1 - Publisher Copyright:
© 2004-2012 IEEE.
PY - 2018/8
Y1 - 2018/8
N2 - This paper presents an area-efficient design of a column-parallel second-order digital decimation filter for a Σ Δ analog-to-digital converter-based CMOS image sensor. By using the proposed pre-bitwise-inversion topology having the same mathematical function, the chip area could be curtailed, where the bit-wise-inversion block, required by the correlated-double-sampling, is moved to the front of the adder. Following such a technique as this, more than six inverters and multiplexers can be reduced. This paper also proposes an adder scheme with only 118 transistors to implement the 13-bit dynamic range integrator. Moreover, the number of MSB cells inside the ripple counter is optimized to balance leakage current and active power consumption. Compared with the prior art, the proposed decimation filter core (without registers) can achieve a reduction of about 24% in transistor count. The proposed design is implemented with a 130-nm standard CMOS process. The total chip area of the digital decimation filter is only $4.5× 145μm2 per column, which is less than half area compared against the prior art. According to the post-layout simulation, the maximum operating frequency is 124 MHz, and the total power consumption, including the filter core and 13-bit registers, is less than 6.35 μW under a typical 50-MHz clock frequency.
AB - This paper presents an area-efficient design of a column-parallel second-order digital decimation filter for a Σ Δ analog-to-digital converter-based CMOS image sensor. By using the proposed pre-bitwise-inversion topology having the same mathematical function, the chip area could be curtailed, where the bit-wise-inversion block, required by the correlated-double-sampling, is moved to the front of the adder. Following such a technique as this, more than six inverters and multiplexers can be reduced. This paper also proposes an adder scheme with only 118 transistors to implement the 13-bit dynamic range integrator. Moreover, the number of MSB cells inside the ripple counter is optimized to balance leakage current and active power consumption. Compared with the prior art, the proposed decimation filter core (without registers) can achieve a reduction of about 24% in transistor count. The proposed design is implemented with a 130-nm standard CMOS process. The total chip area of the digital decimation filter is only $4.5× 145μm2 per column, which is less than half area compared against the prior art. According to the post-layout simulation, the maximum operating frequency is 124 MHz, and the total power consumption, including the filter core and 13-bit registers, is less than 6.35 μW under a typical 50-MHz clock frequency.
KW - CMOS image sensor
KW - area-efficient
KW - column-parallel circuit
KW - digital decimation filter
KW - logic sharing
KW - ΣΔ ADC
UR - http://www.scopus.com/inward/record.url?scp=85043359256&partnerID=8YFLogxK
U2 - 10.1109/TCSI.2018.2795086
DO - 10.1109/TCSI.2018.2795086
M3 - Article
AN - SCOPUS:85043359256
SN - 1549-8328
VL - 65
SP - 2524
EP - 2533
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
IS - 8
ER -