TY - JOUR
T1 - An efficient VLSI architecture and FPGA implementation of the Finite Ridgelet Transform
AU - Chandrasekaran, Shrutisagar
AU - Amira, Abbes
AU - Minghua, Shi
AU - Bermak, Amine
PY - 2008/9
Y1 - 2008/9
N2 - In this paper, an efficient architecture for the Finite Ridgelet Transform (FRIT) suitable for VLSI implementation based on a parallel, systolic Finite Radon Transform (FRAT) and a Haar Discrete Wavelet Transform (DWT) sub-block, respectively is presented. The FRAT sub-block is a novel parametrisable, scalable and high performance core with a time complexity of O(p 2), where p is the block size. Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) implementations are carried out to analyse the performance of the FRIT core developed.
AB - In this paper, an efficient architecture for the Finite Ridgelet Transform (FRIT) suitable for VLSI implementation based on a parallel, systolic Finite Radon Transform (FRAT) and a Haar Discrete Wavelet Transform (DWT) sub-block, respectively is presented. The FRAT sub-block is a novel parametrisable, scalable and high performance core with a time complexity of O(p 2), where p is the block size. Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) implementations are carried out to analyse the performance of the FRIT core developed.
KW - ASIC
KW - FPGA
KW - Finite Radon Transform
KW - Finite Ridgelet Transform
KW - Image processing
KW - VLSI
KW - Wavelets
UR - http://www.scopus.com/inward/record.url?scp=47849115929&partnerID=8YFLogxK
U2 - 10.1007/s11554-008-0081-1
DO - 10.1007/s11554-008-0081-1
M3 - Article
AN - SCOPUS:47849115929
SN - 1861-8200
VL - 3
SP - 183
EP - 193
JO - Journal of Real-Time Image Processing
JF - Journal of Real-Time Image Processing
IS - 3
ER -