Analysis on the Central-stage Buffered Clos-network for packet switching

Our work¹ is motivated by the desire to build a scalable packet switch with extremely large number of ports. We consider building a multi-stage packet switch from many midsize packet switches with distributed memories in the central stage. This new architecture resembles the famous Clos-network used in circuit switching systems except that it has buffers in the central stage. We call it Central-stage Buffered Clos-network (CBC). In particular, we denote the symmetric Clos-network as (n, m, k) which means k input modules with n input ports each and m central modules. Each module is a non-blocking switch. Ideally, this CBC architecture would have similar benefits as those of an output-queued switch, i.e., the delay of individual packets could be precisely controlled, allowing the provision of guaranteed qualities of service. The main result of this paper is that, if m is approximately 4 times that of n, it is theoretically possible for a CBC to emulate an FCFS output-queued packet switch with all components running at the line rate, i.e., with no speedup. Particularly, we need to double the traditional strictly non-blocking Clos-network in the number of central modules. We will show that the need to double the central modules is due to resolving the input port conflicts. But it is still much more cost effective compared with scaling one stage switches which usually have a complexity proportional to the square of the number of ports. If we slightly modify the CBC structure, we can further show that CBC can emulate any QoS queuing discipline if m is approximately 4 times of n. But packets may experience some delay which is bounded within a constant time.