Architecture of a low storage digital pixel sensor array with an on-line block-based compression

Milin Zhang; Amine Bermak

doi:10.1109/DELTA.2008.117

Architecture of a low storage digital pixel sensor array with an on-line block-based compression

Milin Zhang^*, Amine Bermak

^*Corresponding author for this work

Hong Kong University of Science and Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Citation (Scopus)

Abstract

In this paper, a block-based architecture of digital pixel sensor (DPS) array integrated with an on-line compression algorithm is proposed. The proposed technique is based on a block divided storage and compression scheme of the original image. Image capture, storage, and reordering are completed simultaneously and performed on-line while storing pixel value into the on-chip memory array. More than 60% of memory saving is achieved using the proposed block-based design. Furthermore, block-based design greatly reduces the accumulation error inherent in DPCM type of processing. Simulation results show that the PSNR result can reach around 30dB with a compression ratio of less than 3BPP.

Original language	English
Title of host publication	Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008
Pages	167-170
Number of pages	4
DOIs	https://doi.org/10.1109/DELTA.2008.117
Publication status	Published - 2008
Externally published	Yes
Event	4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008 - Hong Kong, SAR, Hong Kong Duration: 23 Jan 2008 → 25 Jan 2008

Publication series

Name	Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008

Conference

Conference	4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008
Country/Territory	Hong Kong
City	Hong Kong, SAR
Period	23/01/08 → 25/01/08

Keywords

Block-based compression
DPS
Error propagation
Low storage

Access to Document

10.1109/DELTA.2008.117

Cite this

Zhang, M., & Bermak, A. (2008). Architecture of a low storage digital pixel sensor array with an on-line block-based compression. In Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008 (pp. 167-170). Article 4459533 (Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008). https://doi.org/10.1109/DELTA.2008.117

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title = "Architecture of a low storage digital pixel sensor array with an on-line block-based compression",

abstract = "In this paper, a block-based architecture of digital pixel sensor (DPS) array integrated with an on-line compression algorithm is proposed. The proposed technique is based on a block divided storage and compression scheme of the original image. Image capture, storage, and reordering are completed simultaneously and performed on-line while storing pixel value into the on-chip memory array. More than 60% of memory saving is achieved using the proposed block-based design. Furthermore, block-based design greatly reduces the accumulation error inherent in DPCM type of processing. Simulation results show that the PSNR result can reach around 30dB with a compression ratio of less than 3BPP.",

keywords = "Block-based compression, DPS, Error propagation, Low storage",

author = "Milin Zhang and Amine Bermak",

year = "2008",

doi = "10.1109/DELTA.2008.117",

language = "English",

isbn = "0769531105",

series = "Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008",

pages = "167--170",

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note = "4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008 ; Conference date: 23-01-2008 Through 25-01-2008",

}

Zhang, M & Bermak, A 2008, Architecture of a low storage digital pixel sensor array with an on-line block-based compression. in Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008., 4459533, Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, pp. 167-170, 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, Hong Kong, SAR, Hong Kong, 23/01/08. https://doi.org/10.1109/DELTA.2008.117

Architecture of a low storage digital pixel sensor array with an on-line block-based compression. / Zhang, Milin; Bermak, Amine.
Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008. 2008. p. 167-170 4459533 (Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - In this paper, a block-based architecture of digital pixel sensor (DPS) array integrated with an on-line compression algorithm is proposed. The proposed technique is based on a block divided storage and compression scheme of the original image. Image capture, storage, and reordering are completed simultaneously and performed on-line while storing pixel value into the on-chip memory array. More than 60% of memory saving is achieved using the proposed block-based design. Furthermore, block-based design greatly reduces the accumulation error inherent in DPCM type of processing. Simulation results show that the PSNR result can reach around 30dB with a compression ratio of less than 3BPP.

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Zhang M, Bermak A. Architecture of a low storage digital pixel sensor array with an on-line block-based compression. In Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008. 2008. p. 167-170. 4459533. (Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008). doi: 10.1109/DELTA.2008.117

Architecture of a low storage digital pixel sensor array with an on-line block-based compression

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