Architecture of three dimensional compressive acquisition CMOS image sensor

In this paper, architecture of a three dimensional (3D) compressive acquisition CMOS image sensor integrated with on-line parallel compression algorithm is proposed. The proposed 3D sensor architecture consists of three hierarchy layers: an image acquisition hierarchy, an image compression hierarchy layer, and an image storage hierarchy layer. The image acquisition hierarchy converts light intensity into current using photodiode. In the second layer, the analog current values are converted into time-slot by comparing with a reference voltage value. The time-slot signal is used in the on-line compression processing. The digital brightest pixel value is used as a reference value, while the differential value between the reference and the raw pixel value is calculated and quantized. The quantized results (typically 2-bit) as well as the reference brightest pixel value are stored in the third hierarchy layer. Compared with standard two dimensional (2D) compressive acquisition CMOS image sensor design, about 70% silicon area is reduced by the 3D integration of different layers. In addition, the increase of the fill factor can be expected as high as near 100%.