Comparative Analysis of Fault-Localization Techniques in Adder

Adder is a complex digital circuit because of its interconnectivity, which hinders fault detection and localization. This paper compares two approaches of fault localization in adders based on carry-free addition using signed digits (SD) representation and localized self-checking-full adders for ripple carry adders (RCA). The self-repairing SD adder approach requires computation with standard and shifted inputs toward left and right for fault localization. The resulting complexity caused by the shifting operation is unnecessary for the self-repairing RCA, which simultaneously achieves fault detection and localization. Moreover, the centralized checking mechanism of the SD adder results in system failure if the checker becomes faulty. However, in the case of self-repairing RCA, the failure of individual full adders will not create problems in the self-checking ability of other full adders owing to the distributed fault detection mechanism. It has been observed that the self-checking RCA implemented in FPGA is 62% more area efficient than the self-checking signed digit adder in terms of LUTs.