Efficient FPGA prototyping of fixed sphere decoder for MIMO systems

Mohamed S. Khairy; Mohamed M. Abdallah; S. E.D. Habib

doi:10.1109/IDT.2008.4802492

Efficient FPGA prototyping of fixed sphere decoder for MIMO systems

Mohamed S. Khairy, Mohamed M. Abdallah, S. E.D. Habib

Cairo University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Citations (Scopus)

Abstract

In this paper, we present a FPGA prototyping of a fixed sphere MIMO decoder as well as a QR implementation of the channel matrix. The FPGA implementation is incorporated with a Matlab simulation model of the MIMO system to validate the hardware design. The proposed design compares favorably to published FPGA implementations of the fixed sphere MIMO decoders, with respect to both the hardware area and throughput metrics. The presented FPGA prototype of the FSD achieves a fixed throughput of 800 Mbps for 4x4 MIMO systems using 16-QAM modulation scheme.

Original language	English
Title of host publication	Proceediangs - 2008 3rd International Design and Test Workshop, IDT 2008
Pages	177-181
Number of pages	5
DOIs	https://doi.org/10.1109/IDT.2008.4802492
Publication status	Published - 2008
Externally published	Yes
Event	2008 3rd International Design and Test Workshop, IDT 2008 - Monastir, Tunisia Duration: 20 Dec 2008 → 22 Dec 2008

Publication series

Name	Proceedings - 2008 3rd International Design and Test Workshop, IDT 2008

Conference

Conference	2008 3rd International Design and Test Workshop, IDT 2008
Country/Territory	Tunisia
City	Monastir
Period	20/12/08 → 22/12/08

Keywords

FPGA prototyping
MIMO systems
Sphere decoder
Wireless communications

Access to Document

10.1109/IDT.2008.4802492

Cite this

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title = "Efficient FPGA prototyping of fixed sphere decoder for MIMO systems",

abstract = "In this paper, we present a FPGA prototyping of a fixed sphere MIMO decoder as well as a QR implementation of the channel matrix. The FPGA implementation is incorporated with a Matlab simulation model of the MIMO system to validate the hardware design. The proposed design compares favorably to published FPGA implementations of the fixed sphere MIMO decoders, with respect to both the hardware area and throughput metrics. The presented FPGA prototype of the FSD achieves a fixed throughput of 800 Mbps for 4x4 MIMO systems using 16-QAM modulation scheme.",

keywords = "FPGA prototyping, MIMO systems, Sphere decoder, Wireless communications",

author = "Khairy, {Mohamed S.} and Abdallah, {Mohamed M.} and Habib, {S. E.D.}",

year = "2008",

doi = "10.1109/IDT.2008.4802492",

language = "English",

isbn = "9781424434770",

series = "Proceedings - 2008 3rd International Design and Test Workshop, IDT 2008",

pages = "177--181",

booktitle = "Proceediangs - 2008 3rd International Design and Test Workshop, IDT 2008",

note = "2008 3rd International Design and Test Workshop, IDT 2008 ; Conference date: 20-12-2008 Through 22-12-2008",

}

Khairy, MS, Abdallah, MM & Habib, SED 2008, Efficient FPGA prototyping of fixed sphere decoder for MIMO systems. in Proceediangs - 2008 3rd International Design and Test Workshop, IDT 2008., 4802492, Proceedings - 2008 3rd International Design and Test Workshop, IDT 2008, pp. 177-181, 2008 3rd International Design and Test Workshop, IDT 2008, Monastir, Tunisia, 20/12/08. https://doi.org/10.1109/IDT.2008.4802492

Efficient FPGA prototyping of fixed sphere decoder for MIMO systems. / Khairy, Mohamed S.; Abdallah, Mohamed M.; Habib, S. E.D.
Proceediangs - 2008 3rd International Design and Test Workshop, IDT 2008. 2008. p. 177-181 4802492 (Proceedings - 2008 3rd International Design and Test Workshop, IDT 2008).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - In this paper, we present a FPGA prototyping of a fixed sphere MIMO decoder as well as a QR implementation of the channel matrix. The FPGA implementation is incorporated with a Matlab simulation model of the MIMO system to validate the hardware design. The proposed design compares favorably to published FPGA implementations of the fixed sphere MIMO decoders, with respect to both the hardware area and throughput metrics. The presented FPGA prototype of the FSD achieves a fixed throughput of 800 Mbps for 4x4 MIMO systems using 16-QAM modulation scheme.

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Y2 - 20 December 2008 through 22 December 2008

ER -

Efficient FPGA prototyping of fixed sphere decoder for MIMO systems

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