Abstract
This paper presents novel VLSI interconnection schemes that can be used to `modularize' parallel convolution circuits. Our methodology implements Toom's algorithm and is based on tensor product factorization of linear convolution into three cascaded stages. The resulting networks have very simple modular structure and highly regular topology. Additionally, the proposed networks have very small depth since only a single stage contains multipliers, while the other two stages contain adders only.
Original language | English |
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Pages | 264-267 |
Number of pages | 4 |
Publication status | Published - 1995 |
Externally published | Yes |
Event | Proceedings of the 1995 IEEE Pacific RIM Conference on Communications, Computers, and Signal Processing - Victoria, BC, Can Duration: 17 May 1995 → 19 May 1995 |
Conference
Conference | Proceedings of the 1995 IEEE Pacific RIM Conference on Communications, Computers, and Signal Processing |
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City | Victoria, BC, Can |
Period | 17/05/95 → 19/05/95 |