Efficient Network Folding Techniques for Routing Permutations in VLSI

Network folding is a technique for realizing permutations on N elements using interconnection networks with M input (and output) terminals, where M < N. A major motivation for network folding is the severely limited number of I/O pins in microelectronic packages, such as VLSI chips or multichip module (MCM) packages. Cost overhead and performance degradation due to off-chip communication as well as long on-chip wires may render implementing otherwise good designs infeasible or inefficient. In this paper, an efficient and systematic methodology is proposed for designing folded permutation networks that can route the class of bit-permute-complement (BPC) permutations. In particular, it is shown that any folded BPC permutation network can be constructed using only two stages of uniform-size transpose networks. This results in highly modular structures for BPC networks. The methodology trades off speed (time), with I/O and chip-area.