Abstract
This paper demonstrates how an FPGA-based transformable coprocessor can be used to implement a real-time MPEG-1 video decoder with enhanced features. The transformable coprocessor consists of an FPGA, local static RAM, and a host bus interface built into the FPGA. The gate-limited FPGA core is reconfigured frequently to implement various parts of the video decoding process in real-time. Our results show that, through reconfiguration, FPGA-based processors can handle complex tasks (such as high-quality video decoding) adequately. We also identify the major bottlenecks that impede achieving higher speedups with the FPGAs. For MPEG-1 video processing, the major slowdown is caused by the excessive data transfers and bottlenecks due to bus interfaces and lack of sufficient storage in FPGA.
Original language | English |
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Title of host publication | Proceedings of SPIE - The International Society for Optical Engineering |
Editors | John Schewel, Peter M. Athanas, V.Michael Jr. Bove, John Watson |
Pages | 308-320 |
Number of pages | 13 |
Volume | 2914 |
Publication status | Published - 1996 |
Externally published | Yes |
Event | High-Speed Computing, Digital Signal Processing, and Filtering Using Reconfigurable Logic - Boston, MA, USA Duration: 20 Nov 1996 → 21 Nov 1996 |
Conference
Conference | High-Speed Computing, Digital Signal Processing, and Filtering Using Reconfigurable Logic |
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City | Boston, MA, USA |
Period | 20/11/96 → 21/11/96 |