High fill-factor native logarithmic pixel: Simulation, design and layout optimization

Amine Bermak; Abdesslam Bouzerdoum; Kamran Eshraghian

doi:10.1109/ISCAS.2000.857422

High fill-factor native logarithmic pixel: Simulation, design and layout optimization

Amine Bermak^*, Abdesslam Bouzerdoum, Kamran Eshraghian

^*Corresponding author for this work

Edith Cowan University

Research output: Contribution to journal › Conference article › peer-review

19 Citations (Scopus)

Abstract

In this paper we investigate important issues in the design of the logarithmic CMOS pixel. In particular, much attention is paid to the optimization of pixel performance in terms of output gain, dynamic range, and fill-factor. In order to increase the gain-bandwidth product, we propose to use the native transistor as source follower. The performance of such a pixel is compared with that of conventional logarithmic pixels. It is shown that the native source follower yields a significant increase in the gain-bandwidth product. In addition, we propose a layout floor-planning strategy which allows us to achieve a 46% fill-factor. In order to compare the performance of the proposed pixel with the conventional NMOS and PMOS logarithmic pixels, a VLSI prototype has been realized using 0.7 μm CMOS technology.

Original language	English
Pages (from-to)	V-293-V-296
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	5
DOIs	https://doi.org/10.1109/ISCAS.2000.857422
Publication status	Published - 2000
Externally published	Yes
Event	Proceedings of the IEEE 2000 International Symposium on Circuits and Systems, ISCAS 2000 - Geneva, Switz, Switzerland Duration: 28 May 2000 → 31 May 2000

Access to Document

10.1109/ISCAS.2000.857422

Cite this

@article{893bc35de4644a39a4ce3a1ac5850e51,

title = "High fill-factor native logarithmic pixel: Simulation, design and layout optimization",

abstract = "In this paper we investigate important issues in the design of the logarithmic CMOS pixel. In particular, much attention is paid to the optimization of pixel performance in terms of output gain, dynamic range, and fill-factor. In order to increase the gain-bandwidth product, we propose to use the native transistor as source follower. The performance of such a pixel is compared with that of conventional logarithmic pixels. It is shown that the native source follower yields a significant increase in the gain-bandwidth product. In addition, we propose a layout floor-planning strategy which allows us to achieve a 46% fill-factor. In order to compare the performance of the proposed pixel with the conventional NMOS and PMOS logarithmic pixels, a VLSI prototype has been realized using 0.7 μm CMOS technology.",

author = "Amine Bermak and Abdesslam Bouzerdoum and Kamran Eshraghian",

year = "2000",

doi = "10.1109/ISCAS.2000.857422",

language = "English",

volume = "5",

pages = "V--293--V--296",

journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

issn = "0271-4310",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "Proceedings of the IEEE 2000 International Symposium on Circuits and Systems, ISCAS 2000 ; Conference date: 28-05-2000 Through 31-05-2000",

}

TY - JOUR

T1 - High fill-factor native logarithmic pixel

T2 - Proceedings of the IEEE 2000 International Symposium on Circuits and Systems, ISCAS 2000

AU - Bermak, Amine

AU - Bouzerdoum, Abdesslam

AU - Eshraghian, Kamran

PY - 2000

Y1 - 2000

N2 - In this paper we investigate important issues in the design of the logarithmic CMOS pixel. In particular, much attention is paid to the optimization of pixel performance in terms of output gain, dynamic range, and fill-factor. In order to increase the gain-bandwidth product, we propose to use the native transistor as source follower. The performance of such a pixel is compared with that of conventional logarithmic pixels. It is shown that the native source follower yields a significant increase in the gain-bandwidth product. In addition, we propose a layout floor-planning strategy which allows us to achieve a 46% fill-factor. In order to compare the performance of the proposed pixel with the conventional NMOS and PMOS logarithmic pixels, a VLSI prototype has been realized using 0.7 μm CMOS technology.

AB - In this paper we investigate important issues in the design of the logarithmic CMOS pixel. In particular, much attention is paid to the optimization of pixel performance in terms of output gain, dynamic range, and fill-factor. In order to increase the gain-bandwidth product, we propose to use the native transistor as source follower. The performance of such a pixel is compared with that of conventional logarithmic pixels. It is shown that the native source follower yields a significant increase in the gain-bandwidth product. In addition, we propose a layout floor-planning strategy which allows us to achieve a 46% fill-factor. In order to compare the performance of the proposed pixel with the conventional NMOS and PMOS logarithmic pixels, a VLSI prototype has been realized using 0.7 μm CMOS technology.

UR - http://www.scopus.com/inward/record.url?scp=0033702502&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2000.857422

DO - 10.1109/ISCAS.2000.857422

M3 - Conference article

AN - SCOPUS:0033702502

SN - 0271-4310

VL - 5

SP - V-293-V-296

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

Y2 - 28 May 2000 through 31 May 2000

ER -

High fill-factor native logarithmic pixel: Simulation, design and layout optimization

Abstract

Access to Document

Other files and links

Fingerprint

Cite this