High Logic Density Cyclic Redundancy Check and Forward Error Correction Logic Sharing Encoding Circuit for JESD204C Controller

Cyclic redundancy check (CRC) and Forward error correction (FEC) encoding are widely used in high-speed information transceiver systems such as PCIe, JESD204C and fiber-optic communications to detect or correct errors in data. Traditionally, the CRC and FEC encoding circuits in JESD204C are implemented independently of each other, which consumes a significant amount of hardware resources. Therefore, a high logic density CRC and FEC logic sharing (CFLS) encoding circuit for JESD204C controller is proposed in this paper, and the logic density of the encoding circuit is improved by sharing the registers and common encoding factor (CEF). Meanwhile, a straightforward critical path delay (CPD) calculation method was proposed to assess whether the data transmission delay satisfies the requirements of CFLS circuits. This method is derived in conjunction with the manipulation of the common factor matrix, thus reducing computational complexity. The CFLS encoding circuit proposed in this paper is verified with an FPGA platform, and the results show that the circuit can realize CRC and FEC function with a 21.96% reduction in hardware resources, compared to the traditional methods. The area of the JESD204C controller with CFLS encoding circuits is 0.09 mm2, by using a 40-nm CMOS process, and the power consumption is 24.66 mW according to the post-layout simulation.