Highly parallel VLSI architectures for linear convolution

A. Elnaggar; H. M. Alnuweiri; M. R. Ito

Highly parallel VLSI architectures for linear convolution

A. Elnaggar^*, H. M. Alnuweiri, M. R. Ito

^*Corresponding author for this work

University of British Columbia

Research output: Contribution to journal › Conference article › peer-review

2 Citations (Scopus)

Abstract

This paper presents highly parallel VLSI structures for linear convolution. Our methodology implements Toom's algorithm and is based on mapping a modified version of the tensor product factorization proposed by Granata et. al. [4]. The resulting networks have very simple structure, highly regular topology, and use simple bit-serial devices. Additionally, the proposed networks have very small depth and contain only a single stage of multipliers, while all other stages contain adders only.

Original language	English
Pages (from-to)	1424-1427
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2
Publication status	Published - 1995
Externally published	Yes
Event	Proceedings of the 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95. Part 3 (of 3) - Seattle, WA, USA Duration: 30 Apr 1995 → 3 May 1995

Cite this

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title = "Highly parallel VLSI architectures for linear convolution",

abstract = "This paper presents highly parallel VLSI structures for linear convolution. Our methodology implements Toom's algorithm and is based on mapping a modified version of the tensor product factorization proposed by Granata et. al. [4]. The resulting networks have very simple structure, highly regular topology, and use simple bit-serial devices. Additionally, the proposed networks have very small depth and contain only a single stage of multipliers, while all other stages contain adders only.",

author = "A. Elnaggar and Alnuweiri, {H. M.} and Ito, {M. R.}",

year = "1995",

language = "English",

volume = "2",

pages = "1424--1427",

journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

issn = "0271-4310",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "Proceedings of the 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95. Part 3 (of 3) ; Conference date: 30-04-1995 Through 03-05-1995",

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TY - JOUR

T1 - Highly parallel VLSI architectures for linear convolution

AU - Elnaggar, A.

AU - Alnuweiri, H. M.

AU - Ito, M. R.

PY - 1995

Y1 - 1995

N2 - This paper presents highly parallel VLSI structures for linear convolution. Our methodology implements Toom's algorithm and is based on mapping a modified version of the tensor product factorization proposed by Granata et. al. [4]. The resulting networks have very simple structure, highly regular topology, and use simple bit-serial devices. Additionally, the proposed networks have very small depth and contain only a single stage of multipliers, while all other stages contain adders only.

AB - This paper presents highly parallel VLSI structures for linear convolution. Our methodology implements Toom's algorithm and is based on mapping a modified version of the tensor product factorization proposed by Granata et. al. [4]. The resulting networks have very simple structure, highly regular topology, and use simple bit-serial devices. Additionally, the proposed networks have very small depth and contain only a single stage of multipliers, while all other stages contain adders only.

UR - http://www.scopus.com/inward/record.url?scp=0029181036&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0029181036

SN - 0271-4310

VL - 2

SP - 1424

EP - 1427

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

T2 - Proceedings of the 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95. Part 3 (of 3)

Y2 - 30 April 1995 through 3 May 1995

ER -

Highly parallel VLSI architectures for linear convolution

Abstract

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