iPIFO: A network memory architecture for QoS routers

Feng Wang*, Mounir Hamdi

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Citations (Scopus)

Abstract

Routers need memories to store and forward packets. More than that, routers use memories to schedule flows according to their quality-of-service (QoS) requirements. The simple first-in-first-out (FIFO) queue memory is insufficient to provide QoS guarantees. Most current routers are based on the virtual-output-queue (VOQ) memory management and use heuristic algorithms, such as iSLIP or DRRM, to schedule packets. On the other hand, push-in-first-out (PIFO) queue memory has also been proposed as a model for routers to meet the QoS requirements. The PIFO queue does not need a scheduler since packets are always first-out from the queue head. However, due to the sorting-related problems of the push-in operation, it is normally supposed impractical to build the PIFO queues in real hardware. We try to touch this problem in this paper and propose an indexed PIFO queue (iPIFO) architecture and a memory management algorithm on it. We believe it is a feasible solution to bring the PIFO queue to practice.

Original languageEnglish
Title of host publication2007 IEEE Workshop on High Performance Switching and Routing, HPSR
Pages217-221
Number of pages5
DOIs
Publication statusPublished - 2007
Externally publishedYes
Event2007 IEEE Workshop on High Performance Switching and Routing, HPSR - Brooklyn, NY, United States
Duration: 30 May 20071 Jun 2007

Publication series

Name2007 IEEE Workshop on High Performance Switching and Routing, HPSR

Conference

Conference2007 IEEE Workshop on High Performance Switching and Routing, HPSR
Country/TerritoryUnited States
CityBrooklyn, NY
Period30/05/071/06/07

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