TY - GEN
T1 - iPIFO
T2 - 2007 IEEE Workshop on High Performance Switching and Routing, HPSR
AU - Wang, Feng
AU - Hamdi, Mounir
PY - 2007
Y1 - 2007
N2 - Routers need memories to store and forward packets. More than that, routers use memories to schedule flows according to their quality-of-service (QoS) requirements. The simple first-in-first-out (FIFO) queue memory is insufficient to provide QoS guarantees. Most current routers are based on the virtual-output-queue (VOQ) memory management and use heuristic algorithms, such as iSLIP or DRRM, to schedule packets. On the other hand, push-in-first-out (PIFO) queue memory has also been proposed as a model for routers to meet the QoS requirements. The PIFO queue does not need a scheduler since packets are always first-out from the queue head. However, due to the sorting-related problems of the push-in operation, it is normally supposed impractical to build the PIFO queues in real hardware. We try to touch this problem in this paper and propose an indexed PIFO queue (iPIFO) architecture and a memory management algorithm on it. We believe it is a feasible solution to bring the PIFO queue to practice.
AB - Routers need memories to store and forward packets. More than that, routers use memories to schedule flows according to their quality-of-service (QoS) requirements. The simple first-in-first-out (FIFO) queue memory is insufficient to provide QoS guarantees. Most current routers are based on the virtual-output-queue (VOQ) memory management and use heuristic algorithms, such as iSLIP or DRRM, to schedule packets. On the other hand, push-in-first-out (PIFO) queue memory has also been proposed as a model for routers to meet the QoS requirements. The PIFO queue does not need a scheduler since packets are always first-out from the queue head. However, due to the sorting-related problems of the push-in operation, it is normally supposed impractical to build the PIFO queues in real hardware. We try to touch this problem in this paper and propose an indexed PIFO queue (iPIFO) architecture and a memory management algorithm on it. We believe it is a feasible solution to bring the PIFO queue to practice.
UR - http://www.scopus.com/inward/record.url?scp=47649099635&partnerID=8YFLogxK
U2 - 10.1109/HPSR.2007.4281241
DO - 10.1109/HPSR.2007.4281241
M3 - Conference contribution
AN - SCOPUS:47649099635
SN - 1424412064
SN - 9781424412068
T3 - 2007 IEEE Workshop on High Performance Switching and Routing, HPSR
SP - 217
EP - 221
BT - 2007 IEEE Workshop on High Performance Switching and Routing, HPSR
Y2 - 30 May 2007 through 1 June 2007
ER -