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Abstract
Linear decimation filters for incremental delta-sigma analog to digital converters are provided with a data rate signal input; a digital signal input; a weight generator connected to the signal input to generate a weight signal via a weight signal output; an adder having a digital signal output, a first addition input connected to the weight signal output, and a second addition input connected to the digital signal output; and an AND-gate having a first input connected to the input data rate signal input and a second input connected to the digital signal input to produce a logical output that gates output from the digital signal output of the adder.
| Original language | English |
|---|---|
| Patent number | US2024178819 |
| IPC | H03K 19/ 20 A I |
| Priority date | 15/11/23 |
| Publication status | Published - 30 May 2024 |
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Dive into the research topics of 'LINEAR DECIMATION FILTERS FOR INCREMENTAL DELTA-SIGMA ANALOG TO DIGITAL CONVERTERS'. Together they form a unique fingerprint.Projects
- 1 Finished
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EX-QNRF-NPRPS-46: Endpoint Secured Multisensor Interface Chip for IoT Applications
Wang, B. (Lead Principal Investigator), Awan, M. A. (Research Assistant), Student-4, G. (Graduate Student), Sunar, P. B. (Principal Investigator) & Ahmad, K. B. A. (Research Assistant)
10/06/21 → 10/12/24
Project: Applied Research