TY - GEN
T1 - Low-power and high-speed current-mode CMOS imager with 1T biasing scheme
AU - Tang, Fang
AU - Bermak, Amine
PY - 2010
Y1 - 2010
N2 - A low-power and high-speed current-mode CMOS image sensor is proposed in this paper. Only one column-level transistor is used in the read-out circuit as a current conveyor to bias the in-pixel transistor operating in triode region. As a result, the current-mode read-out circuit is significantly simplified by the proposed structure, while saving the power by more than half. The proposed scheme enables less than 20ns output settling time due to very low impedance at the internal high capacitance bus, leading to fast operating speed. In addition, a relevant CDS technique is also proposed in order to reduce the first order coefficient variation. A test structure is fabricated using a CMOS 0.35μm process.
AB - A low-power and high-speed current-mode CMOS image sensor is proposed in this paper. Only one column-level transistor is used in the read-out circuit as a current conveyor to bias the in-pixel transistor operating in triode region. As a result, the current-mode read-out circuit is significantly simplified by the proposed structure, while saving the power by more than half. The proposed scheme enables less than 20ns output settling time due to very low impedance at the internal high capacitance bus, leading to fast operating speed. In addition, a relevant CDS technique is also proposed in order to reduce the first order coefficient variation. A test structure is fabricated using a CMOS 0.35μm process.
UR - http://www.scopus.com/inward/record.url?scp=79951878966&partnerID=8YFLogxK
U2 - 10.1109/ICSENS.2010.5689949
DO - 10.1109/ICSENS.2010.5689949
M3 - Conference contribution
AN - SCOPUS:79951878966
SN - 9781424481682
T3 - Proceedings of IEEE Sensors
SP - 1653
EP - 1656
BT - IEEE Sensors 2010 Conference, SENSORS 2010
T2 - 9th IEEE Sensors Conference 2010, SENSORS 2010
Y2 - 1 November 2010 through 4 November 2010
ER -