Lower-power TSPC-based domino logic circuit design with 2/3 clock load

In this paper, we propose a low-power true single-phase-clock (TSPC) based domino logic circuit design. Compared to using three clock transistors in the conventional TSPC-based scheme, the proposed circuit only requires two transistors. As a result, the clock load capacitance is reduced, leading to low power consumption in the clock distribution network. A keeper design to solve charge sharing is also demonstrated. Simulation results using 90nm and 45nm CMOS technologies are provided and discussed, respectively, which illustrate power saving as compared to conventional design not only when the input logic is active but also when the input logic is held to zero.