Matching the speed gap between SRAM and DRAM

Feng Wang*, Mounir Hamdi

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

8 Citations (Scopus)

Abstract

With the constantly increasing Internet traffic, buffers are becoming major bottlenecks for today's high-end routers. In particular, router buffers are required to have both high speed and large capacities, which are hard to build with current single memory technology, such as SRAM or DRAM. A general approach is to make a combination of the SRAM and DRAM and exploit advantages from both. The main obstacle is to find a way matching the speed gap between them. And the requirement to maintain multiple flows in the system further complicates the problem. In this paper, we first investigate previous solutions that use different access granularities to match the speed gap. We point out their intrinsic scaling problems when the number of flows increases. Then, we propose to use parallelism to match the speed gap. Numerical studies and simulations both show that our proposal can theoretically support any number of flows in the router with just little SRAM under practical traffic. In addition, the memory management algorithm is also more scalable compared to those in previous solutions.

Original languageEnglish
Title of host publication2008 International Conference on High Performance Switching and Routing, HPSR 2008
Pages104-109
Number of pages6
DOIs
Publication statusPublished - 2008
Externally publishedYes
Event2008 International Conference on High Performance Switching and Routing, HPSR 2008 - Shanghai, China
Duration: 15 May 200817 May 2008

Publication series

Name2008 International Conference on High Performance Switching and Routing, HPSR 2008

Conference

Conference2008 International Conference on High Performance Switching and Routing, HPSR 2008
Country/TerritoryChina
CityShanghai
Period15/05/0817/05/08

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