TY - GEN
T1 - Matching the speed gap between SRAM and DRAM
AU - Wang, Feng
AU - Hamdi, Mounir
PY - 2008
Y1 - 2008
N2 - With the constantly increasing Internet traffic, buffers are becoming major bottlenecks for today's high-end routers. In particular, router buffers are required to have both high speed and large capacities, which are hard to build with current single memory technology, such as SRAM or DRAM. A general approach is to make a combination of the SRAM and DRAM and exploit advantages from both. The main obstacle is to find a way matching the speed gap between them. And the requirement to maintain multiple flows in the system further complicates the problem. In this paper, we first investigate previous solutions that use different access granularities to match the speed gap. We point out their intrinsic scaling problems when the number of flows increases. Then, we propose to use parallelism to match the speed gap. Numerical studies and simulations both show that our proposal can theoretically support any number of flows in the router with just little SRAM under practical traffic. In addition, the memory management algorithm is also more scalable compared to those in previous solutions.
AB - With the constantly increasing Internet traffic, buffers are becoming major bottlenecks for today's high-end routers. In particular, router buffers are required to have both high speed and large capacities, which are hard to build with current single memory technology, such as SRAM or DRAM. A general approach is to make a combination of the SRAM and DRAM and exploit advantages from both. The main obstacle is to find a way matching the speed gap between them. And the requirement to maintain multiple flows in the system further complicates the problem. In this paper, we first investigate previous solutions that use different access granularities to match the speed gap. We point out their intrinsic scaling problems when the number of flows increases. Then, we propose to use parallelism to match the speed gap. Numerical studies and simulations both show that our proposal can theoretically support any number of flows in the router with just little SRAM under practical traffic. In addition, the memory management algorithm is also more scalable compared to those in previous solutions.
UR - http://www.scopus.com/inward/record.url?scp=60649120277&partnerID=8YFLogxK
U2 - 10.1109/HSPR.2008.4734429
DO - 10.1109/HSPR.2008.4734429
M3 - Conference contribution
AN - SCOPUS:60649120277
SN - 9781424419821
T3 - 2008 International Conference on High Performance Switching and Routing, HPSR 2008
SP - 104
EP - 109
BT - 2008 International Conference on High Performance Switching and Routing, HPSR 2008
T2 - 2008 International Conference on High Performance Switching and Routing, HPSR 2008
Y2 - 15 May 2008 through 17 May 2008
ER -