On fully differential incremental ∆σ ADC with initial feedback zeroing and 1.5-bit feedback

Bo Wang; Man Kay Law; Amine Bermak

On fully differential incremental ∆σ ADC with initial feedback zeroing and 1.5-bit feedback

Bo Wang, Man Kay Law, Amine Bermak

CSE Information & Computing Technology

State Key Laboratory of Analog and Mixed-Signal VLSI

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Citation (Scopus)

Abstract

This paper presents the time-domain analysis of a fully differential incremental ∆Σ modulator. Particularly, the influence of the bipolar feedback signal on the quantization noise of the modulator is analyzed, which is overlooked in most IDC designs. Based on the analysis, an initial feedback zeroing scheme is introduced to decrease the quantization noise of the modulator. Moreover, the maximum number of output codeword that can be produced by the modulator is mathematically derived. Following the derivation, a control scheme is proposed to achieve 1.5-bit effective feedback without changing the quantizer and D/A topology. By applying the initial feedback zeroing and 1.5-bit feedback technique, quantization noise of the 1^st- and 2^nd-order modulators analyzed in this paper can be decreased by 4×, with very minor modifications on the modulator's original digital controllers.

Original language	English
Title of host publication	2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728133201
Publication status	Published - 2020
Event	52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Virtual, Online Duration: 10 Oct 2020 → 21 Oct 2020

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2020-October
ISSN (Print)	0271-4310

Conference

Conference	52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020
City	Virtual, Online
Period	10/10/20 → 21/10/20

Keywords

1.5-bit feedback
Fully differential IDC
Incremental delta-sigma analog-to-digital converter
Modulator codeword
Time-domain analysis

Cite this

Wang, B., Law, M. K., & Bermak, A. (2020). On fully differential incremental ∆σ ADC with initial feedback zeroing and 1.5-bit feedback. In 2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings Article 9180394 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2020-October). Institute of Electrical and Electronics Engineers Inc..

@inproceedings{b29117ec39074bbe89eebf0bdd0a15af,

title = "On fully differential incremental ∆σ ADC with initial feedback zeroing and 1.5-bit feedback",

abstract = "This paper presents the time-domain analysis of a fully differential incremental ∆Σ modulator. Particularly, the influence of the bipolar feedback signal on the quantization noise of the modulator is analyzed, which is overlooked in most IDC designs. Based on the analysis, an initial feedback zeroing scheme is introduced to decrease the quantization noise of the modulator. Moreover, the maximum number of output codeword that can be produced by the modulator is mathematically derived. Following the derivation, a control scheme is proposed to achieve 1.5-bit effective feedback without changing the quantizer and D/A topology. By applying the initial feedback zeroing and 1.5-bit feedback technique, quantization noise of the 1st- and 2nd-order modulators analyzed in this paper can be decreased by 4×, with very minor modifications on the modulator's original digital controllers.",

keywords = "1.5-bit feedback, Fully differential IDC, Incremental delta-sigma analog-to-digital converter, Modulator codeword, Time-domain analysis",

author = "Bo Wang and Law, {Man Kay} and Amine Bermak",

note = "Publisher Copyright: {\textcopyright} 2020 IEEE; 52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020 ; Conference date: 10-10-2020 Through 21-10-2020",

year = "2020",

language = "English",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings",

address = "United States",

}

Wang, B, Law, MK & Bermak, A 2020, On fully differential incremental ∆σ ADC with initial feedback zeroing and 1.5-bit feedback. in 2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings., 9180394, Proceedings - IEEE International Symposium on Circuits and Systems, vol. 2020-October, Institute of Electrical and Electronics Engineers Inc., 52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020, Virtual, Online, 10/10/20.

On fully differential incremental ∆σ ADC with initial feedback zeroing and 1.5-bit feedback. / Wang, Bo; Law, Man Kay; Bermak, Amine.
2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2020. 9180394 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2020-October).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - On fully differential incremental ∆σ ADC with initial feedback zeroing and 1.5-bit feedback

AU - Wang, Bo

AU - Law, Man Kay

AU - Bermak, Amine

PY - 2020

Y1 - 2020

N2 - This paper presents the time-domain analysis of a fully differential incremental ∆Σ modulator. Particularly, the influence of the bipolar feedback signal on the quantization noise of the modulator is analyzed, which is overlooked in most IDC designs. Based on the analysis, an initial feedback zeroing scheme is introduced to decrease the quantization noise of the modulator. Moreover, the maximum number of output codeword that can be produced by the modulator is mathematically derived. Following the derivation, a control scheme is proposed to achieve 1.5-bit effective feedback without changing the quantizer and D/A topology. By applying the initial feedback zeroing and 1.5-bit feedback technique, quantization noise of the 1st- and 2nd-order modulators analyzed in this paper can be decreased by 4×, with very minor modifications on the modulator's original digital controllers.

AB - This paper presents the time-domain analysis of a fully differential incremental ∆Σ modulator. Particularly, the influence of the bipolar feedback signal on the quantization noise of the modulator is analyzed, which is overlooked in most IDC designs. Based on the analysis, an initial feedback zeroing scheme is introduced to decrease the quantization noise of the modulator. Moreover, the maximum number of output codeword that can be produced by the modulator is mathematically derived. Following the derivation, a control scheme is proposed to achieve 1.5-bit effective feedback without changing the quantizer and D/A topology. By applying the initial feedback zeroing and 1.5-bit feedback technique, quantization noise of the 1st- and 2nd-order modulators analyzed in this paper can be decreased by 4×, with very minor modifications on the modulator's original digital controllers.

KW - 1.5-bit feedback

KW - Fully differential IDC

KW - Incremental delta-sigma analog-to-digital converter

KW - Modulator codeword

KW - Time-domain analysis

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M3 - Conference contribution

AN - SCOPUS:85109285150

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

BT - 2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020

Y2 - 10 October 2020 through 21 October 2020

ER -

On fully differential incremental ∆σ ADC with initial feedback zeroing and 1.5-bit feedback

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