On Low-Leakage CMOS Switches

Bo Wang, Shiwei Wang, Man Kay Law

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Citations (Scopus)

Abstract

Continuing CMOS process scaling to favor the design of high-performance digital systems has resulted in many issues for precision analog design, and one of which is the detrimental transistor leakage. This paper focuses on the analysis and design of low-leakage switches. Specifically, transistor leak-age mechanisms and the evolution of low-leakage switch design techniques are revisited. Different schemes to achieve transistor channel and body leakage reduction are discussed. In addition, we propose a low-leakage switch that can operate for a wide temperature range. At 200 C, it achieves 130 × and 8 × lower leakage than the transmission gate and the popular analog T-switch, respectively.

Original languageEnglish
Title of host publication2021 IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2021 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages571-574
Number of pages4
ISBN (Electronic)9781665424615
DOIs
Publication statusPublished - 9 Aug 2021
Event2021 IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2021 - Virtual, East Lansing, United States
Duration: 9 Aug 202111 Aug 2021

Publication series

NameMidwest Symposium on Circuits and Systems
Volume2021-August
ISSN (Print)1548-3746

Conference

Conference2021 IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2021
Country/TerritoryUnited States
CityVirtual, East Lansing
Period9/08/2111/08/21

Keywords

  • CMOS switch
  • CMOS switch array
  • low-leakage CMOS switch
  • transistor leakage compensation

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