TY - GEN
T1 - Open the box of digital neuromorphic processor
T2 - 56th IEEE International Symposium on Circuits and Systems, ISCAS 2023
AU - Tang, Guangzhi
AU - Safa, Ali
AU - Shidqi, Kevin
AU - Detterer, Paul
AU - Traferro, Stefano
AU - Konijnenburg, Mario
AU - Sifalakis, Manolis
AU - Van Schaik, Gert Jan
AU - Yousefzadeh, Amirreza
N1 - Publisher Copyright:
© 2023 IEEE.
PY - 2023
Y1 - 2023
N2 - Sparse and event-driven spiking neural network (SNN) algorithms are the ideal candidate solution for energy-efficient edge computing. Yet, with the growing complexity of SNN algorithms, it isn't easy to properly benchmark and optimize their computational cost without hardware in the loop. Although digital neuromorphic processors have been widely adopted to benchmark SNN algorithms, their black-box nature is problematic for algorithm-hardware co-optimization. In this work, we open the black box of the digital neuromorphic processor for algorithm designers by presenting the neuron processing instruction set and detailed energy consumption of the SENeCA neuromorphic architecture. For convenient benchmarking and optimization, we provide the energy cost of the essential neuromorphic components in SENeCA, including neuron models and learning rules. Moreover, we exploit the SENeCA's hierarchical memory and exhibit an advantage over existing neuromorphic processors. We show the energy efficiency of SNN algorithms for video processing and online learning, and demonstrate the potential of our work for optimizing algorithm designs. Overall, we present a practical approach to enable algorithm designers to accurately benchmark SNN algorithms and pave the way towards effective algorithm-hardware co-design.
AB - Sparse and event-driven spiking neural network (SNN) algorithms are the ideal candidate solution for energy-efficient edge computing. Yet, with the growing complexity of SNN algorithms, it isn't easy to properly benchmark and optimize their computational cost without hardware in the loop. Although digital neuromorphic processors have been widely adopted to benchmark SNN algorithms, their black-box nature is problematic for algorithm-hardware co-optimization. In this work, we open the black box of the digital neuromorphic processor for algorithm designers by presenting the neuron processing instruction set and detailed energy consumption of the SENeCA neuromorphic architecture. For convenient benchmarking and optimization, we provide the energy cost of the essential neuromorphic components in SENeCA, including neuron models and learning rules. Moreover, we exploit the SENeCA's hierarchical memory and exhibit an advantage over existing neuromorphic processors. We show the energy efficiency of SNN algorithms for video processing and online learning, and demonstrate the potential of our work for optimizing algorithm designs. Overall, we present a practical approach to enable algorithm designers to accurately benchmark SNN algorithms and pave the way towards effective algorithm-hardware co-design.
KW - Network
UR - http://www.scopus.com/inward/record.url?scp=85167718193&partnerID=8YFLogxK
U2 - 10.1109/ISCAS46773.2023.10181505
DO - 10.1109/ISCAS46773.2023.10181505
M3 - Conference contribution
AN - SCOPUS:85167718193
T3 - Ieee International Symposium On Circuits And Systems
BT - 2023 Ieee International Symposium On Circuits And Systems, Iscas
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 21 May 2023 through 25 May 2023
ER -