Optimal bounded-degree VLSI networks for sorting in a constant number of rounds

The author presents novel designs of optimal VLSI sorters which combine rotate-sort with enumeration-sort. One major contribution of the present work is the development of an efficient index-mapping methodology to construct simple reduced-area shuffle networks which are used to permute data between sorting stages. Moreover, the proposed networks which are used to permute data work are amenable to simple partitioning schemes resulting in multiple chip networks in which each chip has a small number of I/O (input/output) pins.