Power bounds and energy efficiency in incremental ΔΣ analog-to-digital converters

Saqib Mohamad; Jie Yuan; Amine Bermak

doi:10.1109/TCSI.2018.2847691

Power bounds and energy efficiency in incremental ΔΣ analog-to-digital converters

Saqib Mohamad^*, Jie Yuan, Amine Bermak

^*Corresponding author for this work

CSE Information & Computing Technology

Hong Kong University of Science and Technology

Research output: Contribution to journal › Article › peer-review

3 Citations (Scopus)

Abstract

Incremental analog-to-digital-converters (IADCs) are variants of ΔΣ ADCs, which have been increasingly used for low-power sensory applications in recent years. Most IADC applications require high resolution and high energy efficiency. In this paper, we present a systematic analysis of IADCs. We derive analytical design equations for practical IADC designs. Process limitations are included in the model as well. The equations are verified with a 14-bit second-order IADC design in a 0.18-μm process. With the design equations, the theoretical energy efficiency bound is derived for IADCs. The efficiency bound is compared with previously reported IADC designs. It is found that the derived bound matches existing designs well.

Original language	English
Article number	8401798
Pages (from-to)	4110-4120
Number of pages	11
Journal	IEEE Transactions on Circuits and Systems I: Regular Papers
Volume	65
Issue number	12
DOIs	https://doi.org/10.1109/TCSI.2018.2847691
Publication status	Published - Dec 2018

Keywords

Analog-digital conversion
CMOS analog integrated circuits
delta-sigma ADC
energy efficiency
incremental ADC
switched-capacitor circuits

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10.1109/TCSI.2018.2847691

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title = "Power bounds and energy efficiency in incremental ΔΣ analog-to-digital converters",

abstract = "Incremental analog-to-digital-converters (IADCs) are variants of ΔΣ ADCs, which have been increasingly used for low-power sensory applications in recent years. Most IADC applications require high resolution and high energy efficiency. In this paper, we present a systematic analysis of IADCs. We derive analytical design equations for practical IADC designs. Process limitations are included in the model as well. The equations are verified with a 14-bit second-order IADC design in a 0.18-μm process. With the design equations, the theoretical energy efficiency bound is derived for IADCs. The efficiency bound is compared with previously reported IADC designs. It is found that the derived bound matches existing designs well.",

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AB - Incremental analog-to-digital-converters (IADCs) are variants of ΔΣ ADCs, which have been increasingly used for low-power sensory applications in recent years. Most IADC applications require high resolution and high energy efficiency. In this paper, we present a systematic analysis of IADCs. We derive analytical design equations for practical IADC designs. Process limitations are included in the model as well. The equations are verified with a 14-bit second-order IADC design in a 0.18-μm process. With the design equations, the theoretical energy efficiency bound is derived for IADCs. The efficiency bound is compared with previously reported IADC designs. It is found that the derived bound matches existing designs well.

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Power bounds and energy efficiency in incremental ΔΣ analog-to-digital converters

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Keywords

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