TY - GEN
T1 - Power Reduction in Incremental ΔΣ ADCs Using a Capacitor Scaling Technique
AU - Mohamad, Saqib
AU - Ahmed, Moaaz
AU - Yuan, Jie
AU - Bermak, Amine
N1 - Publisher Copyright:
© 2018 IEEE.
PY - 2018/4/26
Y1 - 2018/4/26
N2 - Incremental analog to digital converters (IADCs) are aimed at converting low frequency signals with high accuracy. The operational transconductance amplifiers (OTAs) used to implement the integrators are the dominant source of power consumption, since they must settle to a desired accuracy within a given clock period, by driving a capacitive load. Reducing the capacitor size correspondingly increases the thermal noise power which reduces the signal-to-noise ratio (SNR) of the ADC. In this paper, we introduce a capacitor scaling technique which exploits the uneven weightage of the IADC decimation filter on the output bit-stream of the IADC. The power consumption can be scaled down correspondingly but the noise power does not increase by the same extent, leading to greater energy efficiency. A second order feedforward IADC is simulated to demonstrate the idea, which achieves up to a 25% improvement in energy efficiency using the proposed scheme.
AB - Incremental analog to digital converters (IADCs) are aimed at converting low frequency signals with high accuracy. The operational transconductance amplifiers (OTAs) used to implement the integrators are the dominant source of power consumption, since they must settle to a desired accuracy within a given clock period, by driving a capacitive load. Reducing the capacitor size correspondingly increases the thermal noise power which reduces the signal-to-noise ratio (SNR) of the ADC. In this paper, we introduce a capacitor scaling technique which exploits the uneven weightage of the IADC decimation filter on the output bit-stream of the IADC. The power consumption can be scaled down correspondingly but the noise power does not increase by the same extent, leading to greater energy efficiency. A second order feedforward IADC is simulated to demonstrate the idea, which achieves up to a 25% improvement in energy efficiency using the proposed scheme.
UR - http://www.scopus.com/inward/record.url?scp=85057093587&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2018.8351289
DO - 10.1109/ISCAS.2018.8351289
M3 - Conference contribution
AN - SCOPUS:85057093587
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
BT - 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018
Y2 - 27 May 2018 through 30 May 2018
ER -