Reduced-complexity mimo detector with close-to ml error rate performance

Maximum likelihood (ML) detection provides optimum error rate performance for uncoded multiple-input multiple-output (MIMO) systems. However, circuit complexity of a straightforward implementation of ML detection is uneconomic for high-rate systems. This paper addresses the VLSI implementation trade-offs of a MIMO detection algorithm that achieves close-to ML error rate performance with reduced computational complexity. The described implementations in a 0.25 m CMOS technology for 4-4 MIMO systems feature a simple data-path, achieve high throughput, and use small silicon area. Important contributing factors to these results are efficient enumeration strategies and the application of simplified norms and sophisticated scheduling techniques together with a new low-complexity preprocessing scheme.