TY - GEN
T1 - Routing BPC permutations in VLSI
AU - Alnuweiri, Hussein M.
PY - 1992
Y1 - 1992
N2 - A large number of the permutations realized by interconnection networks in parallel processing systems and digital arithmetic circuits, fall in the class of bit-permute-complement (BPC) permutations. This paper presents a methodology for routing this class of permutations in VLSI, under various I/O, area, and time trade-offs. The resulting VLSI designs can route a BPC permutation of size N, using a chip with N/Q I/O pins, O(N2/Q2) area, and O(wQ) time, where w is the word length of the permuted elements and 1≤Q≤√N/w.
AB - A large number of the permutations realized by interconnection networks in parallel processing systems and digital arithmetic circuits, fall in the class of bit-permute-complement (BPC) permutations. This paper presents a methodology for routing this class of permutations in VLSI, under various I/O, area, and time trade-offs. The resulting VLSI designs can route a BPC permutation of size N, using a chip with N/Q I/O pins, O(N2/Q2) area, and O(wQ) time, where w is the word length of the permuted elements and 1≤Q≤√N/w.
UR - http://www.scopus.com/inward/record.url?scp=0026962464&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:0026962464
SN - 0818626720
T3 - Proceedings of the International Conference on Parallel Processing
SP - 116
EP - 119
BT - Proceedings of the International Conference on Parallel Processing
PB - Publ by IEEE
T2 - Proceedings of the 6th International Parallel Processing Symposium
Y2 - 23 March 1992 through 26 March 1992
ER -