Scalable router memory architecture based on interleaved DRAM

Routers need buffers to store and forward packets, especially when there is network congestion. With current memory technology, neither the SRAM nor the DRAM alone is suitable for high-speed Internet routers which require both large capacity and fast access time. Some previous work has been done to combine the two technologies together and make a hybrid memory system [1]. In this paper¹, we propose another hybrid memory system based on the interleaved DRAM memories. We devise an efficient memory management algorithm to provide hard performance guarantees to the memory system. The main contribution of this architecture is that it can scale to a very large capacity with interleaved DRAM while only employing necessary SRAM of the same size as in [1]. Another advantage of this architecture is that the interleaved DRAM provides flexibilities to make the memory management algorithms efficient and the memory system very responsive at high speed rates.