Shunting inhibition-based on-chip processing for CMOS imagers

F. Boussaid; A. Bermak; A. Bouzerdoum

doi:10.1109/ICONIP.2002.1202833

Shunting inhibition-based on-chip processing for CMOS imagers

F. Boussaid, A. Bermak, A. Bouzerdoum

Edith Cowan University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Citation (Scopus)

Abstract

Biologically inspired shunting inhibition-based processing is shown to improve significantly the performance of conventional CMOS imagers in terms of dynamic range, sensitivity adaptation but also to provide image processing capabilities such as edge detection and image enhancement. A CMOS imager architecture using current-mode pixels and computation on readout is proposed, which enables shunting inhibition-based processing to be integrated on-chip with the pixels. Fully programmable, the architecture is based on a simple set of externally-tunable parameters that define the imager transfer characteristic, dynamic range compression and sensitivity as well as the type of image processing task requested.

Original language	English
Title of host publication	ICONIP 2002 - Proceedings of the 9th International Conference on Neural Information Processing
Subtitle of host publication	Computational Intelligence for the E-Age
Editors	Jagath C. Rajapakse, Soo-Young Lee, Lipo Wang, Kunihiko Fukushima, Xin Yao
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1310-1314
Number of pages	5
ISBN (Electronic)	9810475241, 9789810475246
DOIs	https://doi.org/10.1109/ICONIP.2002.1202833
Publication status	Published - 2002
Externally published	Yes
Event	9th International Conference on Neural Information Processing, ICONIP 2002 - Singapore, Singapore Duration: 18 Nov 2002 → 22 Nov 2002

Publication series

Name	ICONIP 2002 - Proceedings of the 9th International Conference on Neural Information Processing: Computational Intelligence for the E-Age
Volume	3

Conference

Conference	9th International Conference on Neural Information Processing, ICONIP 2002
Country/Territory	Singapore
City	Singapore
Period	18/11/02 → 22/11/02

Access to Document

10.1109/ICONIP.2002.1202833

Cite this

Boussaid, F., Bermak, A., & Bouzerdoum, A. (2002). Shunting inhibition-based on-chip processing for CMOS imagers. In J. C. Rajapakse, S.-Y. Lee, L. Wang, K. Fukushima, & X. Yao (Eds.), ICONIP 2002 - Proceedings of the 9th International Conference on Neural Information Processing: Computational Intelligence for the E-Age (pp. 1310-1314). Article 1202833 (ICONIP 2002 - Proceedings of the 9th International Conference on Neural Information Processing: Computational Intelligence for the E-Age; Vol. 3). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICONIP.2002.1202833

Boussaid, F. ; Bermak, A. ; Bouzerdoum, A. / Shunting inhibition-based on-chip processing for CMOS imagers. ICONIP 2002 - Proceedings of the 9th International Conference on Neural Information Processing: Computational Intelligence for the E-Age. editor / Jagath C. Rajapakse ; Soo-Young Lee ; Lipo Wang ; Kunihiko Fukushima ; Xin Yao. Institute of Electrical and Electronics Engineers Inc., 2002. pp. 1310-1314 (ICONIP 2002 - Proceedings of the 9th International Conference on Neural Information Processing: Computational Intelligence for the E-Age).

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title = "Shunting inhibition-based on-chip processing for CMOS imagers",

abstract = "Biologically inspired shunting inhibition-based processing is shown to improve significantly the performance of conventional CMOS imagers in terms of dynamic range, sensitivity adaptation but also to provide image processing capabilities such as edge detection and image enhancement. A CMOS imager architecture using current-mode pixels and computation on readout is proposed, which enables shunting inhibition-based processing to be integrated on-chip with the pixels. Fully programmable, the architecture is based on a simple set of externally-tunable parameters that define the imager transfer characteristic, dynamic range compression and sensitivity as well as the type of image processing task requested.",

author = "F. Boussaid and A. Bermak and A. Bouzerdoum",

note = "Publisher Copyright: {\textcopyright} 2002 Nanyang Technological University.; 9th International Conference on Neural Information Processing, ICONIP 2002 ; Conference date: 18-11-2002 Through 22-11-2002",

year = "2002",

doi = "10.1109/ICONIP.2002.1202833",

language = "English",

series = "ICONIP 2002 - Proceedings of the 9th International Conference on Neural Information Processing: Computational Intelligence for the E-Age",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "1310--1314",

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Boussaid, F, Bermak, A & Bouzerdoum, A 2002, Shunting inhibition-based on-chip processing for CMOS imagers. in JC Rajapakse, S-Y Lee, L Wang, K Fukushima & X Yao (eds), ICONIP 2002 - Proceedings of the 9th International Conference on Neural Information Processing: Computational Intelligence for the E-Age., 1202833, ICONIP 2002 - Proceedings of the 9th International Conference on Neural Information Processing: Computational Intelligence for the E-Age, vol. 3, Institute of Electrical and Electronics Engineers Inc., pp. 1310-1314, 9th International Conference on Neural Information Processing, ICONIP 2002, Singapore, Singapore, 18/11/02. https://doi.org/10.1109/ICONIP.2002.1202833

Shunting inhibition-based on-chip processing for CMOS imagers. / Boussaid, F.; Bermak, A.; Bouzerdoum, A.
ICONIP 2002 - Proceedings of the 9th International Conference on Neural Information Processing: Computational Intelligence for the E-Age. ed. / Jagath C. Rajapakse; Soo-Young Lee; Lipo Wang; Kunihiko Fukushima; Xin Yao. Institute of Electrical and Electronics Engineers Inc., 2002. p. 1310-1314 1202833 (ICONIP 2002 - Proceedings of the 9th International Conference on Neural Information Processing: Computational Intelligence for the E-Age; Vol. 3).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - Biologically inspired shunting inhibition-based processing is shown to improve significantly the performance of conventional CMOS imagers in terms of dynamic range, sensitivity adaptation but also to provide image processing capabilities such as edge detection and image enhancement. A CMOS imager architecture using current-mode pixels and computation on readout is proposed, which enables shunting inhibition-based processing to be integrated on-chip with the pixels. Fully programmable, the architecture is based on a simple set of externally-tunable parameters that define the imager transfer characteristic, dynamic range compression and sensitivity as well as the type of image processing task requested.

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Boussaid F, Bermak A , Bouzerdoum A. Shunting inhibition-based on-chip processing for CMOS imagers. In Rajapakse JC, Lee SY, Wang L, Fukushima K, Yao X, editors, ICONIP 2002 - Proceedings of the 9th International Conference on Neural Information Processing: Computational Intelligence for the E-Age. Institute of Electrical and Electronics Engineers Inc. 2002. p. 1310-1314. 1202833. (ICONIP 2002 - Proceedings of the 9th International Conference on Neural Information Processing: Computational Intelligence for the E-Age). doi: 10.1109/ICONIP.2002.1202833

Shunting inhibition-based on-chip processing for CMOS imagers

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